High speed serial interface test

• US 20040250187A1
• Filed: 06/09/2003
• Published: 12/09/2004
• Est. Priority Date: 06/09/2003
• Status: Active Grant

• Current Assignee: NetApp, Inc.
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Campbell, Kevin, Schauer, Steven
• Granted Patent: US 7,082,557 B2
• Time in Patent Office: Days
• US Class Current: 714/728
• CPC Class Codes: H04L 12/42 Loop networks

Abstract

A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.

Claims

1. A method of testing a serial interface comprising:

storing an output word into a first register;

creating an output stream by repeatedly recalling said output word from said first register;

passing said output stream through a scrambler to create a first pseudo-random sequence within said output stream;

passing said output stream through a transmitter;

looping said output stream back into a receiver;

passing said output stream through a descrambler to descramble said first pseudo-random sequence within said output stream to generate multiple input words;

comparing each of said multiple input words to said output word in said first register to determine any errors;

storing said errors into an error register; and

evaluating the performance of said serial interface by at least in part evaluating said errors in said error register.

2. The method of claim 1 further comprising:

passing said first pseudo-random output stream through an encoder to encode said output stream; and

passing said first pseudo-random output stream through a decoder to decode said output stream.

3. The method of claim 1 further comprising:

sending a start sequence from said scrambler to said descrambler, wherein said descrambler is adapted to receive said start sequence and is capable of synchronizing with said scrambler based on said start sequence.

4. The method of claim 1 further comprising:

setting said scrambler into a bypass mode wherein said pseudo-random sequence is not created within said output stream; and

setting said descrambler into a bypass mode wherein said pseudo-random sequence is not descrambled within said output stream.

5. The method of claim 2 further comprising:

setting said encoder into a bypass mode wherein said output stream is not encoded; and

setting said decoder into a bypass mode wherein said output stream is not decoded.

6. A serial interface with internal testing comprising:

a register capable of storing an output word;

a sequencer capable of recalling said output word from said register to create an output stream;

a scrambler capable of receiving said output stream and scrambling said output stream to create a pseudo-random sequence within said output stream;

a transmitter capable of transmitting said output stream on an output line;

a receiver capable of receiving said output stream on an input line;

a loop back path capable of switching said output line to said input line such that said transmitter and said receiver are in communication;

a descrambler capable of receiving said output stream and descrambling said pseudo-random sequence to generate multiple input words; and

a comparator capable of comparing each of said multiple input words with said output word stored in said register, said comparator further capable of detecting an error if one of said input words is not the same as said output word and logging said error.

7. The serial interface of claim 6 further comprising:

an encoder capable of receiving said output stream and encoding said output stream; and

a decoder capable of receiving said output stream and decoding said output stream.

8. The serial interface of claim 6 wherein said descrambler is adapted to receive a start sequence and is capable of synchronizing with said scrambler based on said start sequence.

9. The serial interface of claim 6 wherein:

said scrambler is capable of a bypass mode wherein said pseudo-random sequence is not created within said output stream; and

said descrambler is capable of a bypass mode wherein said pseudo-random sequence is not descrambled within said output stream.

10. The serial interface of claim 7 wherein:

said encoder is capable of a bypass mode wherein said output stream is not encoded; and

said decoder is capable of a bypass mode wherein said output stream is not decoded.