Methods and apparatus for packaging integrated circuit devices
First Claim
Patent Images
1. An integrally packaged integrated circuit device comprising:
- an integrated circuit die comprising;
a crystalline substrate having first and second generally planar surfaces and edge surfaces; and
an active surface formed on said first generally planar surface;
at least one chip scale packaging layer formed over said active surface; and
at least one electrical contact formed over said at least one chip scale packaging layer, said at least one electrical contact being connected to circuitry on said active surface by at least one pad formed on said first generally planar surface.
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Abstract
An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
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Citations
39 Claims
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1. An integrally packaged integrated circuit device comprising:
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an integrated circuit die comprising;
a crystalline substrate having first and second generally planar surfaces and edge surfaces; and
an active surface formed on said first generally planar surface;
at least one chip scale packaging layer formed over said active surface; and
at least one electrical contact formed over said at least one chip scale packaging layer, said at least one electrical contact being connected to circuitry on said active surface by at least one pad formed on said first generally planar surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of producing integrally packaged integrated circuit devices comprising:
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providing a plurality of integrated circuit dies formed on a wafer, each of said dies having first and second generally planar surfaces, and an active surface and at least one pad formed on said first generally planar surface, said active surface including circuitry;
forming at least one chip scale packaging layer over said active surface;
forming at least one electrical contact over said at least one chip scale packaging layer, said at least one electrical contact being connected to said circuitry by said at least one pad; and
subsequently dicing said wafer to define a plurality of packaged integrated circuit devices. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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Specification