MEMORY MODULE AND METHOD HAVING IMPROVED SIGNAL ROUTING TOPOLOGY
First Claim
1. A memory module, comprising:
- a plurality of memory devices;
an active memory component having a plurality of input terminals and a plurality of output terminals; and
a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree comprising at least one branch, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end.
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Accused Products
Abstract
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.
138 Citations
34 Claims
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1. A memory module, comprising:
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a plurality of memory devices;
an active memory component having a plurality of input terminals and a plurality of output terminals; and
a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree comprising at least one branch, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory module, comprising:
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a plurality of memory devices;
an active memory component having a plurality of input terminals and a plurality of output terminals; and
a plurality of transmission lines coupling a plurality of the output terminals of the active memory device to respective input terminals of the memory devices, each of the transmission lines being connected at only its ends to either one of the input terminals of one of the memory devices or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having the same length. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A processor-based system, comprising:
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a processor having a processor bus;
a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;
at least one input device coupled to the peripheral device port of the system controller;
at least one output device coupled to the peripheral device port of the system controller;
at least one data storage device coupled to the peripheral device port of the system controller; and
a memory module coupled to the system memory port of the system controller, the memory module comprising;
a plurality of memory devices;
an active memory component having a plurality of input terminals and a plurality of output terminals; and
a symmetrical tree coupling each of several of the output terminals of the active memory component to respective input terminals of the memory devices, the symmetrical tree comprising at least one branch, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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- 28. A method of coupling signals from an active memory component in a memory module to a plurality of memory devices in the memory module, the method comprising coupling a plurality of the signals from the active memory component to the memory devices through a plurality of transmission lines in which each transmission line is connected at only its ends to either one of the memory devices or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having the same length.
Specification