Tracker architecture for GPS systems

• US 20040252049A1
• Filed: 07/18/2002
• Published: 12/16/2004
• Est. Priority Date: 07/18/2001
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Peng, Leon Kuo-Liang, Turetzky, Gregory, Vantalon, Nicolas
• Granted Patent: US 7,091,904 B2
• Time in Patent Office: Days
• US Class Current: 342/357.06
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/35 Constructional details or hardware or software details of the signal processing chain
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: G01S 19/46 the supplementary measurement being of a radio-wave signal type

Abstract

A tracker architecture for Global Positioning System (GPS) receivers is disclosed. A typical tracker comprises an RF front end and GPS architecture. The architecture comprises a bus structure, a Central Processing Unit (CPU) core, cache, RAM, and ROM memories, and a GPS engine that comprises a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals. The GPS architecture can couple to at least two different protocol interfaces via the bus structure, where the protocol interfaces are commonly used in different applications.

Claims

1. A Global Positioning System (GPS) architecture used for tracking at least one GPS satellite, comprising:

a bus structure,

a Central Processing Unit (CPU) core comprising a microprocessor, coupled to the bus structure;

a cache memory coupled to the bus structure for storing software code;

a random access memory, coupled to the bus structure, for storing data;

a read only memory, coupled to the bus structure, for storing a boot program; and

a GPS engine, comprising;

a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals,

wherein the GPS architecture can couple to at least two different protocol interfaces via the bus structure.

2. The GPS architecture of claim 1, wherein the cache memory can be used as a local random access memory.

3. The GPS architecture of claim 2, wherein the CPU can be used for running applications other than GPS tracking.

4. The GPS architecture of claim 3, wherein the GPS engine further comprises a beacon processor.

5. The GPS architecture of claim 3, wherein the GPS engine runs on a separate bus structure.

6. The GPS architecture of claim 5, wherein the GPS engine further comprises inputs from a real time clock external to the GPS engine.

7. The GPS architecture of claim 6, further comprising a bus interface unit.

8. The GPS architecture of claim 7, wherein the protocol interfaces are selected from a group comprising I2C, CAN, PWM, SPI, J1850, USB, GPIO, MOST, parallel, and an address/data bus interface.

9. The GPS architecture of claim 8, wherein the protocol interface is selected a priori.

10. The GPS architecture of claim 8, wherein the protocol interface is selected by the GPS architecture through sensing a signal in the protocol interface.

11. A Global Positioning System (GPS) architecture used for tracking at least one GPS satellite, comprising:

a bus structure,

a Central Processing Unit (CPU) core comprising a microprocessor, coupled to the bus structure;

a cache memory coupled to the bus structure for storing software code;

a random access memory, coupled to the bus structure, for storing data and for storing autonomous code used for tracking at least one GPS satellite;

a read only memory, coupled to the bus structure, for storing a boot program; and

a GPS engine, comprising;

a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals,

wherein the GPS engine can selectively use the stored autonomous code for tracking at least one GPS satellite.

12. The GPS architecture of claim 11, wherein the architecture can couple, via the bus structure, to at least two different protocol interfaces, selected from a group comprising I2C, CAN, PWM, SPI, J1850, USB, GPIO, MOST, parallel, and an address/data bus interface.

13. The GPS architecture of claim 12, wherein the cache memory can be used as a local random access memory.

14. The GPS architecture of claim 13, wherein the CPU can be used for running applications other than GPS tracking.

15. The GPS architecture of claim 14, wherein the GPS engine further comprises a beacon processor.

16. The GPS architecture of claim 14, wherein the GPS engine runs on a separate bus structure.

17. The GPS architecture of claim 16, wherein the GPS engine further comprises inputs from a real time clock external to the GPS engine.

18. The GPS architecture of claim 17, further comprising a bus interface unit.

19. The GPS architecture of claim 17, wherein the protocol interface is selected a priori.

20. The GPS architecture of claim 17, wherein the protocol interface is selected by the GPS architecture through sensing a signal in the protocol interface.

21. A Global Positioning System (GPS) architecture used for tracking at least one GPS satellite, comprising:

a bus structure,

a Central Processing Unit (CPU) core comprising a microprocessor, coupled to the bus structure;

a cache memory coupled to the bus structure for storing software code;

a random access memory, coupled to the bus structure, for storing data;

a read only memory, coupled to the bus structure, for storing a boot program; and

a GPS engine, comprising;

a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals,

wherein the GPS architecture can couple, via the bus structure, to at least two different protocol interfaces, and wherein the protocol interface is selected by the GPS architecture automatically.