Route aware serial advanced technology attachment (SATA) switch
First Claim
Patent Images
1. A switch coupled between a plurality of host units and a device for routing frame information therebetween and comprising:
- a. a first serial advanced technology attachment (ATA) port, including a route aware frame information structure (FIS) coupled to a first host unit;
b. a second serial ATA port, including a route aware FIS, coupled to a second host unit;
c. a third serial ATA port, including a route aware FIS, coupled to a device; and
d. an arbitration and control circuit for selecting one of the first host or second host units to be coupled to the device, through the switch, whenever either one of the first or second host units sends FIS to the device and further wherein the FIS of the first and second host units and the device identify which one of the first or second host units is an origin and/or destination host so that routing of FIS is transparent to the switch thereby reducing the complexity of the design of the switch rendering its manufacturing less expensive.
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Abstract
An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.
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Citations
19 Claims
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1. A switch coupled between a plurality of host units and a device for routing frame information therebetween and comprising:
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a. a first serial advanced technology attachment (ATA) port, including a route aware frame information structure (FIS) coupled to a first host unit;
b. a second serial ATA port, including a route aware FIS, coupled to a second host unit;
c. a third serial ATA port, including a route aware FIS, coupled to a device; and
d. an arbitration and control circuit for selecting one of the first host or second host units to be coupled to the device, through the switch, whenever either one of the first or second host units sends FIS to the device and further wherein the FIS of the first and second host units and the device identify which one of the first or second host units is an origin and/or destination host so that routing of FIS is transparent to the switch thereby reducing the complexity of the design of the switch rendering its manufacturing less expensive. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 13)
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9. A switch comprising:
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a. a first serial advanced technology attachment (ATA) port, including a route aware frame information structure (FIS), for connection to a first host unit;
b. a second serial ATA port, including a route aware FIS, for connection to a second host unit;
c. a third serial ATA port, including a route aware FIS, for connection to a device, the switch for routing frame information between the first and second host units and the device; and
d. an arbitration and control circuit for selecting either the first host unit or the second host unit to be coupled to the device, through the switch, when either one of the first or second host units sends FIS to the device, wherein while one of the first or second host units is coupled to the device, through the switch, the other one of the first or second host units sends FIS to the switch for routing to the device and further wherein the FIS of the first and second host units and the device identify which one of the first or second host units is an origin and/or destination host so that routing of FIS is transparent to the switch thereby reducing the complexity of the design of the switch rendering its manufacturing less expensive. - View Dependent Claims (10, 11, 12)
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14. A switch that is connectable to a first host unit, a second host unit and a device via serial advanced technology attachment (ATA) links, for routing frame information between the first and second host units and the device, said switch comprising:
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a. a first serial ATA port, including a route aware frame information structure (FIS), for connection to a first host unit;
b. a second serial ATA port, including a route aware FIS, for connection to a second host unit;
c. a third serial ATA port, including a route aware FIS, for connection to a device;
d. an arbitration and control circuit for selecting one of the first or second host units to be coupled to the device through the switch when either the first or second host units sends FIS to the device, wherein while one of the first or second host units is coupled to the device, the other one of to the first or second host units sends FIS to the switch for routing to the device and further wherein the FIS of the first and second host units and the device identify which one of the first or second host units is an origin and/or destination host so that routing of FIS is transparent to the switch thereby reducing the complexity of the design of the switch rendering its manufacturing less expensive. - View Dependent Claims (15, 16, 17, 18)
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19. A method for communication between multiple host units and a device, through a serial advanced technology attachment (ATA) switch coupled to the multiple host units and the device using serial ATA links routing frame information therebetween, comprising:
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a. coupling a first serial ATA port, including a route aware frame information structure (FIS), to a first host unit for connection to the switch;
b. coupling a second serial ATA port, including a route aware FIS, to a second host unit for connection to the switch;
c. coupling a third serial ATA port, including a route aware FIS, for connection to a device;
d. arbitrating between the first and second host units and the device;
e. selecting one of the first or second host units for coupling to the device through the switch when either of the first or second host units sends commands for execution by the device;
f. coupling the device to the selected one of the first or second host units; and
g. while the selected one of the first or second host units is coupled to the device, the other one of the first or second host units sending FIS to the switch for routing to the device during the sending step g., the FIS of the first and second host units and the device identifying which one of the first or second host units is an origin and/or destination host so that routing of FIS is transparent to the switch thereby reducing the complexity of the design of the switch rendering its manufacturing less expensive.
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Specification