Route aware serial advanced technology attachment (SATA) switch

• US 20040252672A1
• Filed: 02/09/2004
• Published: 12/16/2004
• Est. Priority Date: 06/11/2003
• Status: Active Grant

• Current Assignee: NetApp, Inc.
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Nemazie, Sam
• Granted Patent: US 7,539,797 B2
• Time in Patent Office: Days
• US Class Current: 370/351
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.

Claims

1. A switch coupled between a plurality of host units and a device for routing frame information therebetween and comprising:

a. a first serial advanced technology attachment (ATA) port, including a route aware frame information structure (FIS) coupled to a first host unit;

b. a second serial ATA port, including a route aware FIS, coupled to a second host unit;

c. a third serial ATA port, including a route aware FIS, coupled to a device; and

d. an arbitration and control circuit for selecting one of the first host or second host units to be coupled to the device, through the switch, whenever either one of the first or second host units sends FIS to the device and further wherein the FIS of the first and second host units and the device identify which one of the first or second host units is an origin and/or destination host so that routing of FIS is transparent to the switch thereby reducing the complexity of the design of the switch rendering its manufacturing less expensive.

2. A switch as recited in claim 1 wherein said device is a storage unit.

3. A switch as recited in claim 1 wherein said switch is employed in an enterprise system.

4. A switch as recited in claim 1 wherein said arbitration and control circuit causes concurrent access of the device by the first and second host units.

5. A switch as recited in claim 1 wherein a bit is used to indicate which host is the origin or destination of the FIS.

6. A switch as recited in claim 1 wherein said first, second and third ports are layer 2 ports.

7. A switch as recited in claim 1 wherein the switch provides for ‘

route aware’

routing.

8. A switch as recited in claim 1 wherein the switch switches between layer and includes a dual ported first-in-first-out (FIFO).

13. A switch as recited in claim 1 wherein said arbitration and control causes concurrent access of the device by the first and second host units.

9. A switch comprising:

a. a first serial advanced technology attachment (ATA) port, including a route aware frame information structure (FIS), for connection to a first host unit;

b. a second serial ATA port, including a route aware FIS, for connection to a second host unit;

c. a third serial ATA port, including a route aware FIS, for connection to a device, the switch for routing frame information between the first and second host units and the device; and

d. an arbitration and control circuit for selecting either the first host unit or the second host unit to be coupled to the device, through the switch, when either one of the first or second host units sends FIS to the device,

wherein while one of the first or second host units is coupled to the device, through the switch, the other one of the first or second host units sends FIS to the switch for routing to the device and further wherein the FIS of the first and second host units and the device identify which one of the first or second host units is an origin and/or destination host so that routing of FIS is transparent to the switch thereby reducing the complexity of the design of the switch rendering its manufacturing less expensive.

10. A switch as recited in claim 9 wherein the switch is a serial ATA switch.

11. A switch as recited in claim 9 wherein said device is a storage unit.

12. A switch as recited in claim 9 wherein said switch is employed in an enterprise system.

14. A switch that is connectable to a first host unit, a second host unit and a device via serial advanced technology attachment (ATA) links, for routing frame information between the first and second host units and the device, said switch comprising:

a. a first serial ATA port, including a route aware frame information structure (FIS), for connection to a first host unit;

b. a second serial ATA port, including a route aware FIS, for connection to a second host unit;

c. a third serial ATA port, including a route aware FIS, for connection to a device;

d. an arbitration and control circuit for selecting one of the first or second host units to be coupled to the device through the switch when either the first or second host units sends FIS to the device,

wherein while one of the first or second host units is coupled to the device, the other one of to the first or second host units sends FIS to the switch for routing to the device and further wherein the FIS of the first and second host units and the device identify which one of the first or second host units is an origin and/or destination host so that routing of FIS is transparent to the switch thereby reducing the complexity of the design of the switch rendering its manufacturing less expensive.

15. A switch as recited in claim 14 wherein the switch is a serial ATA switch.

16. A switch as recited in claim 14 wherein said device is a storage unit.

17. A switch as recited in claim 14 wherein said switch is employed in an enterprise system.

18. A switch as recited in claim 14 wherein said arbitration and control circuit causes concurrent access of the device by the first and second host units.

19. A method for communication between multiple host units and a device, through a serial advanced technology attachment (ATA) switch coupled to the multiple host units and the device using serial ATA links routing frame information therebetween, comprising:

a. coupling a first serial ATA port, including a route aware frame information structure (FIS), to a first host unit for connection to the switch;

b. coupling a second serial ATA port, including a route aware FIS, to a second host unit for connection to the switch;

c. coupling a third serial ATA port, including a route aware FIS, for connection to a device;

d. arbitrating between the first and second host units and the device;

e. selecting one of the first or second host units for coupling to the device through the switch when either of the first or second host units sends commands for execution by the device;

f. coupling the device to the selected one of the first or second host units; and

g. while the selected one of the first or second host units is coupled to the device, the other one of the first or second host units sending FIS to the switch for routing to the device

during the sending step g., the FIS of the first and second host units and the device identifying which one of the first or second host units is an origin and/or destination host so that routing of FIS is transparent to the switch thereby reducing the complexity of the design of the switch rendering its manufacturing less expensive.