Multi-channel line interface unit with on-chip clock management

• US 20040252800A1
• Filed: 06/13/2003
• Published: 12/16/2004
• Est. Priority Date: 06/13/2003
• Status: Abandoned Application

• Current Assignee: Vitesse Semiconductor Corp (Microchip Technology Incorporated)
• Original Assignee: Vitesse Semiconductor Corp (Microchip Technology Incorporated)
• Inventors: Kota, Kishore, Paulos, John James
• Application Number:
  US10/462,214
• Publication Number:
  US 20040252800A1
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Multi-channel line interface unit with on-chip clock management. A method for clocking a multi-channel Line Interface Unit (LIU) embodied in an integrated circuit and having a plurality of channels is disclosed. Each channel has a receive path and a transmit path. An reference clock input is provided for receiving an external reference clock signal. A free running on-chip clock is generated that is synchronized to the reference clock signal. On at least two of the channels, transmit or receive data clocks and associated corresponding transmit and receive data operating at an associated data rate are received. Transmit and receive data are processed on each of the respective channels with a portion of the processing occurring in the digital domain. A separate channel clock is generat from the free running clock for each of the at least two channels and synchronized to the respective received transmit or receive data clocks and referenced to the free running on-chip clock, such that the received transmit or receive data clocks can be independent of each other and referenced to a single external reference signal. A controller is operable to utilize the respective separate channel clock by the digital portion of the step of processing in the respective channel.

Claims

1. A method for clocking a multi-channel Line Interface Unit (LIU) embodied in an integrated circuit and having a plurality of channels, each having a receive path and a transmit path, comprising the steps of:

receiving an external reference clock signal;

generating a free running on-chip clock synchronized to the reference clock signal;

receiving on at least two of the channels transmit or receive data clocks and associated corresponding transmit and receive data operating at an associated data rate;

processing the transmit and receive data on each of the respective channels with a portion of the processing occurring in the digital domain;

generating from the free running clock a separate channel clock for each of the at least two channels and synchronized to the respective received transmit or receive data clocks and referenced to the free running on-chip clock, such that the received transmit or receive data clocks can be independent of each other and referenced to a single external reference signal; and

utilizing the respective separate channel clock by the digital portion of the step of processing in the respective channel.

2. The method of claim 1, wherein the step of generating the free running clock comprises the steps of:

generating an on-chip frequency source; and

phase locking the on-chip frequency source to the received external reference signal.

3. The method of claim 2, wherein the step of phase locking includes the step of comparing the phase of the external reference signal to the phase of the on-chip frequency source and generating a phase error which is then filtered with a loop filter with a defined filter response to generate a control signal that varies the frequency of the on-chip frequency source to minimize the phase error until a lock condition occurs and providing a plurality of phase increments of the free running clock.

4. The method of claim 3, wherein the step of generating each of the separate channel clocks comprises the steps of:

receiving the associated transmit or receive clock;

generating a variable channel clock that is phase referenced to the incremental phase increments of the free running clock with a frequency independent thereof, and

phase synchronizing the received associated transmit or receive clock with the variable channel clock of the associated channel.

5. The method of claim 4, where the free running clock is an oversampled free running clock with a frequency of a predetermined proportion of the external reference signal.

6. The method of claim 5, wherein the variable channel clock for each of the channels operates at a frequency substantially the same as the free running clock.

7. The method of claim 6, wherein channels with differing data rates have associated variable channel clocks with different frequencies.

8. The method of claim 6, and comprising the step of dividing the frequency of the variable channel clock for a given one of the channels by a set factor to substantially equal the data rate associated with the given one of the channels.

9. The method of claim 8, wherein the set factor is different for channels associated with different data rates.

10. The Method of claim 9, wherein the set factor can be substantially the same as the predetermined proportion when the associated data rate is substantially equal to the external reference signal.

11. The method of claim 5, wherein the step of phase synchronizing the received associated transmit or receive clock with the variable channel clock of the associated channel comprises the steps of:

selecting for each of the generated separate channel clocks select ones of the generated multiple phases of the oversampled free running clock; and

utilizing the selected phases to generate the associated one of the variable channel clocks operating at substantially the same frequency as the oversampled free running clock.

12. The method of claim 5, and further comprising the step of generating a free running variable clock that is phase referenced to the incremental phase increments of the free running clock with a frequency independent thereof and that operates at a frequency substantially the same as the frequency of the oversampled free running clock and dividing the frequency thereof by a set factor to provide an output free running clock signal that can have a frequency different than the frequency of the external reference clock signal.

13. The method of claim 4, and further comprising the step of reclocking the transmit or receive data with the associated received transmit or receive clock.

14. The method of claim 13, wherein the step of reclocking comprises the step of processing the transmit or receive data with a jitter attenuator that has data written thereto with the received associated transmit or receive clock and read therefrom with the associated separate channel clock.

15. A clock generator for a multi-channel Line Interface Unit (LIU) embodied in an integrated circuit and having a plurality of channels, each having a receive path and a transmit path, comprising:

a reference clock input for receiving an external reference clock signal;

a reference clock generator for generating a free running on-chip clock synchronized to the external reference clock signal;

each of the channels having transmit and receive paths and at least two of the channels receiving transmit and receive data clocks and associated corresponding transmit and receive data operating at an associated data rate on the associated transmit and receive paths;

a processing section associated with each of the transmit and receive paths for each of the respective channels for processing the transmit and receive data with a portion of the processing occurring in the digital domain;

a channel clock generator for each channel for generating from the free running clock a separate channel clock for each of the at least two channels and synchronized to the respective received transmit or receive data clocks and referenced to the free running on-chip clock, such that the received transmit or receive data clocks can be independent of each other and referenced to a single external reference signal; and

the digital portion of the processing section of each of the channels utilizing the respective separate channel clock processing in the associated digital portion.

16. The clock generator of claim 15, wherein said reference clock generator comprises:

on-chip frequency generator for generating an on-chip frequency source; and

a phase lock loop for phase locking the on-chip frequency source to the received external reference signal.

17. The clock generator of claim 16, said phase lock loop comprises a phase comparator for comparing the phase of the external reference signal to the phase of the on-chip frequency source and generating a phase error which is then filtered with a loop filter with a defined filter response to generate a control signal that varies the frequency of the on-chip frequency source to minimize the phase error until a lock condition occurs and providing a plurality of phase increments of the free running clock.

18. The clock generator of claim 17, wherein said channel clock generator for each of the channels comprises:

a variable channel clock for generating a variable channel clock that is phase referenced to the incremental phase increments of the free running clock with a frequency independent thereof; and

a phase synchronizer for phase synchronizing the received associated transmit or receive clock with the variable channel clock of the associated channel.

19. The clock generator of claim 18, where the free running clock is an oversampled free running clock with a frequency of a predetermined proportion of the external reference clock signal.

20. The clock generator of claim 19, wherein the variable channel clock for each of the channels operates at a frequency substantially the same as the free running clock.

21. The clock generator of claim 20, wherein channels with differing data rates have associated variable channel clocks with different frequencies.

22. The clock generator of claim 20, and further comprising a frequency divider for dividing the frequency of the variable channel clock for a given one of the channels by a set factor to substantially equal the data rate associated with the given one of the channels.

23. The clock generator of claim 22, wherein the set factor is different for channels associated with different data rates.

24. The Clock generator of claim 23, wherein the set factor can be substantially the same as the predetermined proportion when the associated data rate is substantially equal to the external reference clock signal.

25. The clock generator of claim 19, wherein said phase synchronizer comprises:

a phase selector for selecting for each of the generated separate channel clocks select ones of the generated multiple phases of the oversampled free running clock; and

a controller for utilizing the selected phases to generate the associated one of the variable channel clocks operating at substantially the same frequency as the oversampled free running clock.

26. The clock generator of claim 19, and further comprising an output clock generator for generating a free running variable clock that is phase referenced to the incremental phase increments of the free running clock with a frequency independent thereof and that operates at a frequency substantially the same as the frequency of the oversampled free running clock and an output frequency divider for dividing the frequency thereof by a set factor to provide an output free running clock signal that can have a frequency different than the frequency of the external reference clock signal.

27. The clock generator of claim 18, and further comprising a smoothing device for reclocking the transmit or receive data with the associated received transmit or receive clock.

28. The clock generator of claim 27, wherein said smoothing device comprises a jitter attenuator that has data written thereto with the received associated transmit or receive clock and read therefrom with the associated separate channel clock.