Clock and data recovery circuit
First Claim
1. A clock and data recovery circuit having a frequency tracking loop and a phase tracking loop, said clock and data recovery circuit comprising:
- a phase detector comparing a phase of an input data signal with a phase of a synchronous clock signal;
a phase interpolator receiving an input clock signal and a control signal, adjusting a phase of an output clock signal based on the control signal, and supplying the output clock signal to said phase detector as the synchronous clock signal;
said phase detector and said phase interpolator owned in common by said frequency tracking loop and said phase tracking loop;
a pattern generator generating a signal for variably setting the phase of the output clock signal from said phase interpolator based on a result of phase comparison by said phase detector and outputting the so generated signal;
said pattern generator provided in said frequency tracking loop; and
a circuit generating the control signal to said phase interpolator based on a result of phase detection by said phase tracking loop and an output signal of said pattern generator in said frequency tracking loop.
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Accused Products
Abstract
A clock and data recovery circuit, for tracking frequency-modulated input data, comprises a phase detector for receiving a data signal and a synchronous clock signal, detecting a phase delay or a phase advance, and outputting an UP1/DOWN1 signal, first and second integrators for integrating the UP1/DOWN1 signal and outputting an UP2/DOWN2 signal and an UP3/DOWN3 signal, respectively, a pattern generator for receiving the UP3/DOWN3 signal from the second integrator to output an UP4/DOWN4 signal, a mixer for receiving the UP2/DOWN2 signal from the first integrator and the UP4/DOWN4 signal from the pattern generator and generating an UP5/DOWN5 signal for output, and a phase interpolator for interpolating the phase of an input clock signal based on the UP5/DOWN5 signal from the mixer, for output are provided. A clock signal output from the interpolator is fed back to the phase detector as the clock.
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Citations
40 Claims
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1. A clock and data recovery circuit having a frequency tracking loop and a phase tracking loop, said clock and data recovery circuit comprising:
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a phase detector comparing a phase of an input data signal with a phase of a synchronous clock signal;
a phase interpolator receiving an input clock signal and a control signal, adjusting a phase of an output clock signal based on the control signal, and supplying the output clock signal to said phase detector as the synchronous clock signal;
said phase detector and said phase interpolator owned in common by said frequency tracking loop and said phase tracking loop;
a pattern generator generating a signal for variably setting the phase of the output clock signal from said phase interpolator based on a result of phase comparison by said phase detector and outputting the so generated signal;
said pattern generator provided in said frequency tracking loop; and
a circuit generating the control signal to said phase interpolator based on a result of phase detection by said phase tracking loop and an output signal of said pattern generator in said frequency tracking loop. - View Dependent Claims (20, 24, 28, 29, 35, 39, 40)
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2. A clock and data recovery circuit comprising:
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a phase detector receiving a data signal and a synchronous clock signal and, comparing phases of the synchronous clock signal and the data signal and outputting a result of phase comparison; and
a phase interpolator receiving an input clock signal and a control signal and variably adjusting a phase of an output clock signal;
a pattern generator receiving an integrated value of the result of the phase comparison from said phase detector and generating and outputting a signal for variably setting the phase of the output clock signal of said phase interpolator;
said pattern generator provided in a frequency tracking loop; and
a mixer generating a signal obtained by mixing the integrated value in a phase tracking loop with an output signal of said pattern generator in said frequency tracking loop, said phase tracking loop controlling the phase of the output clock signal from said phase interpolator in accordance with the integrated value of the result of the phase comparison by said phase detector;
the mixer supplying the generated signal to said phase interpolator as the control signal;
the output clock signal from said phase interpolator being fed back to said phase detector as the synchronous clock signal. - View Dependent Claims (3, 4, 5, 21, 25, 30, 36)
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6. A clock and data recovery circuit comprising:
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a phase detector receiving a data signal and a synchronous clock signal, comparing phases of the received two signals to detect a delay and an advance, and outputting a first control signal according to a result of the detection;
a first integrator receiving the first control signal output from said phase detector and integrating the received first control signal to output the resultant signal as a second control signal;
a second integrator receiving the first control signal output from said phase detector and integrating the received first control signal to output the resultant signal as a third control signal;
a pattern generator receiving the third control signal from said second integrator, counting the received third control signal and outputting a fourth control signal based on a result of the counting;
a mixer receiving the second control signal from said first integrator and the fourth control signal from said pattern generator and generating a fifth control signal based on the second control signal and the fourth control signal, for output; and
a phase interpolator receiving an input clock signal and the fifth control signal from said mixer, and adjusting a phase of an output clock signal based on the fifth control signal;
the output clock signal from said phase interpolator being fed back to said phase detector as the synchronous clock. - View Dependent Claims (8, 10, 12, 14, 16, 17, 22, 26, 31, 33, 37)
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7. A clock and data recovery circuit comprising:
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a phase detector receiving a data signal and a synchronous clock signal, comparing phases of the received two signals to detect a delay and an advance, and outputting a first control signal according to a result of the detection;
an integrator receiving the first control signal output from said phase detector and integrating the received first control signal to output the resultant signal as a second control signal;
a pattern generator receiving the second control signal from said integrator, counting the received second control signal and outputting a third control signal based on a result of the counting;
a mixer receiving the second control signal from said integrator and the third control signal from said pattern generator, and generating a fourth control signal based on the second control signal and the third control signal to output the so generated signal; and
a phase interpolator receiving an input clock signal and the fourth control signal from said mixer and then adjusting a phase of an output clock signal based on the fourth control signal;
the output clock signal from said phase interpolator being fed back to said phase detector as the synchronous clock signal. - View Dependent Claims (9, 11, 13, 15, 18, 19, 23, 27, 32, 34, 38)
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Specification