MULTI-STEP CHEMICAL MECHANICAL POLISHING OF A GATE AREA IN A FINFET

• US 20040253775A1
• Filed: 06/12/2003
• Published: 12/16/2004
• Est. Priority Date: 06/12/2003
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yu, Bin, Wang, Haihong, Ahmed, Shibly S., Achuthan, Krishnashree
• Granted Patent: US 6,855,607 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: C09G 1/02 containing abrasives or grinding agents abrasives as such C09K3/14; polishing of semi-conductors H01L
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: Y10S 438/959 Mechanical polishing of wafer

Abstract

A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a fin structure on an insulator;

forming a gate structure over at least a portion of the fin structure and a portion of the insulator;

planarizing the gate structure by performing a chemical mechanical polishing (CMP) of the gate structure using a first slurry; and

planarizing the gate structure in a second planarization by performing a CMP of the gate structure using a second slurry different than the first slurry, the second planarization of the gate structure reducing a height of the gate structure above the fin structure in a channel region of the semiconductor device while raising a height of the gate structure surrounding the fin structure.

2. The method of claim 1, further comprising:

forming a source and a drain region adjacent the fin.

3. The method of claim 1, wherein the CMP of the gate structure using the first slurry acts to remove gate material at a faster rate than the CMP of the gate structure using the second slurry.

4. The method of claim 1, wherein, after planarizing the gate structure by performing a CMP of the gate structure using the first slurry, the gate structure extends to 500 Å

to about 1500 Å

over the fin structure in a channel region of the semiconductor device.

5. The method of claim 4, wherein, after planarizing the gate structure by performing a CMP of the gate structure using the second slurry, the gate structure extending to approximately 300 Å

above the fin structure in the channel region of the semiconductor device.

6. The method of claim 1, wherein the semiconductor device is a FinFET.

7. The method of claim 1, wherein the first slurry is a silica based buffering slurry having a pH ranging from about 10.5-11.5 and includes an alkali component at a concentration ranging from about 0.1% to 4%.

8. The method of claim 1, wherein the second slurry is a silica based buffering slurry having a pH ranging from about 10.5-11.5 and includes an alkali component at a concentration ranging from about 0.1% to 1%.

9. The method of claim 1, wherein a removal rate of the gate structure using the second slurry is approximately 200 Å

/minute.

10. A method for forming a MOSFET device comprising:

forming a source, a drain, and a fin structure on an insulating layer, portions of the fin structure acting as a channel for the MOSFET;

forming a dielectric layer around the fin structure;

depositing a polysilicon layer over the fin structure, the polysilicon layer acting as a gate area for the MOSFET;

planarizing the polysilicon layer at a first rate; and

further planarizing the polysilicon layer at a second rate slower than the first rate,

wherein the further planarization of the polysilicon layer reduces a height of the polysilicon layer above the fin structure while raising a height of the polysilicon layer in areas adjacent the fin structure.

11. The method of claim 10, wherein planarizing the polysilicon layer at the first and second rates includes chemical mechanical polishing (CMP) of the polysilicon layer using first and second slurries.

13. The method of claim 10, wherein the MOSFET device is a FinFET.

14. The method of claim 10, wherein the planarizing the polysilicon layer at the first rate removes approximately 800 Å

from the polysilicon layer.

15. The method of claim 10, wherein, after planarizing the polysilicon layer at the second rate, the thickness of the polysilicon layer above the fin structure is approximately 300 Å

.

12. (canceled)

16. A method for forming a MOSFET device comprising:

forming a source region on an insulating layer;

forming a drain region on the insulating layer;

forming a fin structure on the insulating layer, portions of the fin structure acting as a channel for the MOSFET;

depositing a polysilicon layer over at least portions of the fin structure and the insulating layer, the polysilicon layer acting as a gate area for the MOSFET and extending over the fin structure;

performing a first planarization of the polysilicon layer at a first rate; and

performing a second planarization of the polysilicon layer at a second rate slower than the first rate, the second planarization of the polysilicon layer reducing a height of the polysilicon layer over the fin structure while raising a height of the polysilicon layer adjacent the fin structure; and

doping the source and drain regions.

18. The method of claim 16, wherein polishing the polysilicon layer at the first and second rates includes chemical mechanical polishing (CMP) of the polysilicon layer using first and second slurries.

19. The method of claim 16, wherein the MOSFET device is a FinFET.

17. (canceled)