System for identification of defects on circuits or other arrayed products

• US 20040254752A1
• Filed: 06/10/2003
• Published: 12/16/2004
• Est. Priority Date: 06/10/2003
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yashchin, Emmanuel, Trapp, Brian, Takken, Asya, Landers, Christina, Wisniewski, Mary
• Granted Patent: US 7,346,470 B2
• Time in Patent Office: Days
• US Class Current: 702/84
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is selected to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.

Claims

1. A method to assess a probability of failure of operation of a semiconductor wafer comprising:

inputting risk factor data into a memory;

inputting a plurality of wafers into a semiconductor fabrication manufacturing process;

selecting a subset of the plurality of wafers to obtain a sample population of wafers;

inspecting at least one region of each wafer of the sample population of wafers;

obtaining circuit design data associated with each wafer of the sample population of wafers;

identifying one or more defects that present an increased risk to the operation of a particular wafer,

wherein the identifying is a function of the risk factor data, the inspecting step and the circuit design data; and

assessing a probability of semiconductor wafer failure.

2. The method as claimed in claim 1, further comprising:

generating a circuit risk map for the particular wafer as a function of the circuit design data; and

utilizing the circuit risk map in the identifying step.

3. The method as claimed in claim 2, further comprising:

generating a tool inspection area on the particular wafer as a function of the risk map; and

utilizing the tool inspection area in the identifying step.

4. The method as claimed in claim 1, further comprising:

identifying a defect location risk for the particular wafer;

identifying a defect location for the particular wafer;

identifying a defect size for the at least one region; and

utilizing one or more of the defect location risk, defect positional risk and defect size in the identifying step.

5. The method as claimed in claim 1, further comprising:

generating a list of defects that include defect location risk;

generating a probability of wafer failure as a function of the list of defects; and

accumulating the probability of failure of the particular wafer for each step of the manufacturing process.

6. The method as claimed in claim 1, further comprising:

generating a probability of failure of the particular wafer for each identified one or more defects.

7. The method as claimed in claim 1, further comprising:

inputting defect information that relates to the one or more defects;

determining a region on a circuit that contains an associated location of a particular defect;

calculating a failure rate for the particular defect as a function of the design data, the region and the defect information for the particular defect; and

utilizing the failure rate in the identifying step.

8. A method to calculate a risk factor for a region of a wafer comprising:

obtaining circuit design data;

tiling the circuit design data on a surface of the wafer;

identifying location defects on the wafer by utilizing design shapes that are in the region of the defect;

evaluating the location risk; and

determining a failure probability in the region.

9. The method as claimed in claim 8, wherein the step of determining a failure probability is a function of defect parameters.

10. The method as claimed in claim 9, wherein the defect parameters include at least one of defect size, defect classification or defect risk factor.

11. The method as claimed in claim 8, further comprising calculating an adjusted failure probability as a function of failure analysis.

12. The method as claimed in claim 11, further comprising applying the adjusted failure probability to the step of calculating a failure probability.

13. The method as claimed in claim 8, further comprising:

generating a statistical model as a function of a defect type and local design information of a defect to risk, or location risk.

14. The method as claimed in claim 8, further comprising generating a defect list as a function of defects identified on the wafer, wherein the defect list includes at least one of location risk data, location data, defect size data or defect type data.

15. A method of generating a data representation comprising:

generating a graph of circuit design data;

identifying one or more enhanced risk regions of the circuit design data;

identifying one or more defects;

generating data indicative of overlap between the one or more enhanced risk regions and the one or more defects; and

generating data indicative of a quantity of defective circuits.

16. The method as claimed in claim 15, further comprising calculating a risk of failure for a circuit as a function of the quantity of defective circuits.

17. An apparatus for assessing one or more flaws in a circuit comprising:

a calculation module adapted to select a function to calculate a location of risk of the circuit;

a location module adapted to establish a defect location as a function of circuit design data; and

an evaluation module that receives data from the calculation module and the location module, the evaluation module adapted to generate an output as a function of the received data, the output identifies an inspection area of the circuit.

18. The apparatus of claim 17, wherein the evaluation module is adapted to generate the output in real-time.

19. The apparatus of claim 17, wherein the evaluation module is adapted to evaluate a region in proximity to a flaw as a function of a metal fraction.

20. The apparatus of claim 17, wherein the evaluation module is adapted to evaluate a region in proximity to a flaw as a function of a critical area.

21. The apparatus of claim 17, further comprising:

a review module, coupled to the evaluation module, the review module adapted to provide input to the evaluation module that includes review data.

22. The apparatus of claim 17, wherein the evaluation module is provided data related to prior assessments of flaws.

23. An apparatus for assessing one or more flaws in a circuit comprising:

means for selecting a function to calculate a location of risk of the circuit;

means for establishing a defect location as a function of circuit design data; and

means for generating a defect list, the defect list being generated as a function of identified defects, circuit layer data and a region of interest around the identified defects.

24. The apparatus of claim 23, further comprising means for evaluating a region in proximity to a flaw as a function of a metal fraction.

25. The apparatus of claim 23, further comprising means for evaluating a region in proximity to a flaw as a function of a critical area.

26. A method to assess regions of interest of a circuit, the method being implemented with computer instructions stored on a computer-readable medium, comprising:

providing circuit design data;

providing defect data relating to one or more defects;

establishing a region of the circuit that contains a location of the one or more defects;

generating a failure probability as a function of the circuit design data, defect data and location.

27. The method of claim 26, wherein the generating a failure probability is a function of defect size data.

28. The method of claim 26, further comprising:

categorizing particular defects as sampled defects;

classifying the sampled defects as a function of defect characteristics; and

generating a failure probability as a function of the categorizing and classifying steps.

29. A method for evaluating defects in a product that defines an array of components comprising:

inputting risk factor data into a memory;

inspecting at least one region of the product in accordance with the risk factor;

obtaining design data associated with the product;

identifying one or more defects that present an increased risk of failure of the product based on the risk factor data, the design data, and the inspecting.

30. The method of claim 29 further including using the results of identifying one or more defects to update the risk factor data.

31. A method of enabling efficient detection of defects in a product defining an array of sub-components comprising:

populating a database with at least a portion of design information for a product defining an array of sub-components and at least one risk factor related to manufacture of the product;

allowing access over a network to relevant information in the database, wherein the relevant information comprises

design data tailored to the detection of a defect within at least one of a sub-component or a physical portion of the product, and

at least one weighted risk factor that may be used to identify at least one of a type of sub-component or a specific physical portion of the product that is prone to defects.

32. The method of claim 31 further including updating the at least one weighted risk factor based on an actual defect in the product.

33. A computer program embedded on a medium readable by a computer comprising:

a first program code segment that includes design data for a product that defines an array of sub-components;

a second program code segment that includes risk factor data relating to a likelihood of a defect in at least one of a sub-component or a physical location of the product; and

a third program code segment that provides for inputting data related to actual defects discovered in the product.

34. The computer program of claim 33 further comprising:

a fourth program segment that modifies the risk factor data in response to data input through the third program segment related to actual defects discovered.