Low leakage heterojunction vertical transistors and high performance devices thereof
First Claim
1. A method of preparing a vertical channel of a field effect transistor comprising the steps of:
- providing a first p-type single crystalline silicon region with a concentration level greater than 1×
1019 atoms/cm3 on a first substrate, forming a second carbon-doped epitaxial region over said first p-type silicon region, doping said second carbon-doped epitaxial region p-type to a concentration level greater than 1×
1019 atoms/cm3, forming a third silicon region over said second carbon-doped epitaxial region, doping said third silicon region n-type, forming a fourth compressively strained Si1-w-qGewCq epitaxial region over said third silicon region, doping said fourth compressively strained Si1-w-qGewCq region p-type to a concentration level greater than 1×
1019 atoM/cm3, forming a fifth silicon epitaxial region over said fourth compressively strained Si1-w-qGewCq region, doping said fifth silicon epitaxial region p-type to a concentration level greater than 1×
1019 atoms/cm3, forming a vertical structure comprising at least one sidewall extending from said first p-type silicon region, second carbon-doped region, third region of silicon, fourth region of Si1-w-qGewCq epitaxial region, and fifth region of silicon, forming a sixth compressively strained Si1-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region of carbon-doped layer, over said third region of silicon to said fourth compressively strained Si1-w-qGewCq epitaxial region.
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Abstract
A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.
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Citations
88 Claims
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1. A method of preparing a vertical channel of a field effect transistor comprising the steps of:
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providing a first p-type single crystalline silicon region with a concentration level greater than 1×
1019 atoms/cm3 on a first substrate,forming a second carbon-doped epitaxial region over said first p-type silicon region, doping said second carbon-doped epitaxial region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a third silicon region over said second carbon-doped epitaxial region, doping said third silicon region n-type, forming a fourth compressively strained Si1-w-qGewCq epitaxial region over said third silicon region, doping said fourth compressively strained Si1-w-qGewCq region p-type to a concentration level greater than 1×
1019 atoM/cm3,forming a fifth silicon epitaxial region over said fourth compressively strained Si1-w-qGewCq region, doping said fifth silicon epitaxial region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a vertical structure comprising at least one sidewall extending from said first p-type silicon region, second carbon-doped region, third region of silicon, fourth region of Si1-w-qGewCq epitaxial region, and fifth region of silicon, forming a sixth compressively strained Si1-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region of carbon-doped layer, over said third region of silicon to said fourth compressively strained Si1-w-qGewCq epitaxial region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of preparing a vertical channel of a field effect transistor comprising the steps of:
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providing a first p-type single crystalline silicon region with a concentration level greater than 1×
1019 atoms/cm3 on a first substrate,forming a second carbon-doped epitaxial region over said first p-type silicon region, doping said second carbon-doped epitaxial region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a third silicon epitaxial region over said second carbon-doped epitaxial region, doping said third silicon region n-type, forming a fourth compressively strained Si1-w-qGewCq epitaxial region over said third silicon region, doping said fourth compressively strained Si1-w-qGewCq region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a fifth silicon epitaxial region over said fourth compressively strained Si1-w-qGewCq region, doping said silicon epitaxial region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a vertical structure comprising at least one sidewall extending from said first p-type silicon region, second region of carbon-doped layer, third region of silicon, fourth region of Si1-w-qGewCq epitaxial region, and fifth region of silicon, forming a sixth compressively strained Si1-sGes region over a region of said at least one sidewall of said vertical structure extending from said second carbon-doped region, over said third region of silicon to said fourth region of Si1-w-qGewCq epitaxial region, and forming a seventh silicon region over said sixth compressively strained Si1-sGes region. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A method of preparing a vertical channel of a field effect transistor comprising the steps of:
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providing a first p-type single crystalline silicon region with a concentration level greater than 1×
1019 atoms/cm3 on a first substrate,forming a second compressively strained Si1-x-yGexCy epitaxial region over said first silicon region, doping said second Si1-x-yGexCy region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a third silicon epitaxial region over said second region, doping said third region n-type, forming a fourth compressively strained Si1-w-qGewCq epitaxial region over said third silicon epitaxial region, doping said fourth Si1-w-qGewCq epitaxial region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a fifth silicon epitaxial region over said fourth Si1-w-qGewCq epitaxial region, doping said fifth silicon region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a vertical structure comprising at least one sidewall extending from said first silicon region, second region, third silicon epitaxial region, fourth Si1-w-qGewCq epitaxial region, and fifth region, forming a sixth compressively strained Si1-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region, over said third region of silicon to said fourth Si1-w-qGewCq epitaxial region. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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50. A method of preparing an inverter made of the vertical field effect CMOS transistors comprising the steps of:
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forming a first silicon epitaxial region on a first single crystalline substrate, doping said first silicon epitaxial region n-type to a concentration level greater than 1×
1019 atoms/cm3,forming a second Si1-i-jGeiCj epitaxial region over said first n-type silicon region, forming a third silicon epitaxial region over said second Si1-i-jGeiCj region, doping said third silicon epitaxial region p-type, forming a fourth strained Si1-yCy epitaxial region over said third p-type silicon region, doping said fourth strained Si1-yCy region n-type to a concentration level greater than 1×
1019 atoms/cm3,forming a fifth silicon region over said fourth n-type strained Si1-yCy region, doping said fifth silicon region n-type to a concentration level greater than 1×
1019 atoms/cm3,forming a first vertical column structure comprising at least one sidewall extending from said first silicon region, over said second strained Si1-xCx region, over said third region of p-type silicon, over said fourth region of strained Si1-yCy, to said fifth silicon region, forming a sixth silicon region over a region of said at least one sidewall of said first vertical structure, forming a first gate dielectric region over said sixth silicon region, forming a first gate conducting region over said first gate dielectric region, masking and etching a nearby region to expose said first single crystalline substrate, forming a seventh p-type silicon region with a concentration level greater than 1×
1019 atoms/cm3 on said first single crystalline substrate,forming an eighth carbon-doped epitaxial region over said seventh region, doping said eighth region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a ninth silicon epitaxial region over said eighth region, doping said ninth region n-type, forming a tenth compressively strained Si1-w-qGewCq epitaxial region over said ninth region, doping said tenth Si1-w-qGewCq region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming an eleventh silicon epitaxial region over said tenth Si1-w-qGewCq region, doping said eleventh silicon region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a second vertical column structure comprising said seventh silicon region, eighth carbon-doped region, ninth silicon region, tenth Si1-w-qGewCq region, and eleventh silicon epitaxial region, forming a twelvth strained Si1-sGes region over the outer perimeter of the second vertical column structure, forming a second gate dielectric region over the outer perimeter of said twelfth region, forming a second gate conducting region over the outer perimeter of said second gate dielectric region. - View Dependent Claims (51, 52, 53, 54, 55)
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56. A method of preparing an inverter made of the vertical field effect CMOS transistors comprising the steps of:
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forming a first relaxed Si1-iGei epitaxial region on a first single crystalline substrate, doping said first Si1-iGei epitaxial region n-type to a concentration level greater than 1×
1019 atoms/cm3,forming a second carbon-doped SiGe epitaxial region over said first n-type Si1-iGei region, doping said second SiGe epitaxial region n-type to a concentration level greater than 1×
1019 atoms/cm3,forming a third relaxed Si1-iGei epitaxial region over said second carbon-doped SiGe region, doping said third silicon epitaxial region p-type, forming a fourth tensile strained silicon epitaxial region over said third p-type Si1-iGei region, doping said fourth strained silicon region n-type to a concentration level greater than 1×
1019 atoms/cm3,forming a fifth relaxed Si1-iGei region over said fourth n-type strained silicon region, doping said Si1-iGei region n-type to a concentration level greater than 1×
1019 atoms/cm3,forming a first vertical column structure comprising at least one sidewall extending from said first relaxed Si1-iGei region, over said second carbon-doped SiGe region, over said third region of p-type relaxed Si1-iGei, over said fourth strained silicon region to said fifth SiGe region, forming a sixth strained silicon region over a region of said at least one sidewall of said first vertical structure, forming a first gate dielectric region over said sixth silicon region, forming a first gate conducting region over said first gate dielectric region, masking and etching a nearby region to expose said first single crystalline substrate, forming a seventh p-type silicon region with a concentration level greater than 1×
1019 atoms/cm3 on said first single crystalline substrate,forming an eighth carbon-doped epitaxial region over said seventh region, doping said eighth region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a ninth silicon epitaxial region over said eighth region, doping said ninth epitaxial region n-type, forming a tenth compressively strained Si1-w-qGewCq epitaxial region over said ninth epitaxial region, doping said tenth Si1-w-qGewCq region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming an eleventh silicon epitaxial region over said tenth Si1-w-qGewCq region, doping said eleventh silicon epitaxial region p-type to a concentration level greater than 1×
1019 atoms/cm3,forming a second vertical column structure comprising said seventh silicon region, eighth carbon-doped region, ninth silicon epitaxial region, tenth Si1-w-qGewCq region, and eleventh silicon epitaxial region, forming a twelfth strained Si1-sGes region over the outer perimeter of the above second vertical column structure, forming second gate a dielectric region over the outer perimeter of the above twelfth region, and forming a second gate conducting region over the outer perimeter of said second gate dielectric region, - View Dependent Claims (57, 58, 59, 60)
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61. A field effect transistor comprising:
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a substrate, a first single crystalline silicon region having a p-type concentration level greater than 1×
1019 atoms/cm3 on said substrate,a second carbon-doped epitaxial region over said first crystalline silicon region having a p-type concentration level greater than 1×
1019 atoms/cm3,a third silicon epitaxial region over said second carbon-doped region doped n-type, a fourth compressively strained Si1-w-qGewCq epitaxial region over said third silicon epitaxial region, said Si1-w-qGewCq region having a p-type concentration level greater than 1×
1019 atom/cm3,a fifth silicon containing region over said fourth Si1-w-qGewCq region having a p-type concentration level greater than 1×
1019 atoms/cm3,a vertical structure comprising at least one sidewall extending from said first silicon region, second region of carbon-doped layer, third region of silicon, fourth region of Si1-w-qGewCq epitaxial region to said fifth region of silicon, a sixth compressively strained Si1-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region of carbon-doped layer, over said third region of silicon to said fourth region of Si1-w-qGewCq epitaxial region, a gate dielectric region over said sixth compressively strained Si1-sGes region, and a gate conducting region over said dielectric region. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76)
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77. An inverter comprising:
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a first silicon epitaxial region on a first single crystalline substrate having a n-type concentration level greater than 1×
1019 atoms/cm3,a second Si1-i-jGeiCj epitaxial region over said first n-type silicon region, a third silicon epitaxial region over said second Si1-i-jGeiCj epitaxial region doped p-type, a fourth strained Si1-yCy epitaxial region over said third p-type silicon region having a n-type concentration level greater than 1×
1019 atoms/cm3,a fifth region selected from a group consisting of single crystalline silicon, poly silicon and poly SiGe over said fourth n-type strained Si1-yCy region having a n-type concentration level greater than 1×
1019 atoms/cm3,a first vertical structure comprising at least one sidewall extending from said first silicon region, over said second region of strained Si1-xCx region, over said third region of p-type silicon, over said fourth region of strained Si1-yCy to said fifth region, a sixth silicon region over a region of said at least one sidewall of said vertical structure, a first gate dielectric region over said sixth silicon region, and a first gate conducting region over said gate dielectric region, a seventh p-type silicon epitaxial region on said first single crystalline substrate having a concentration level greater than 1×
1019 atoms/cm3,an eighth carbon-doped epitaxial region over said seventh p-type silicon epitaxial region having a p-type to a concentration level greater than 1×
1019 atoms/cm3,a ninth silicon epitaxial region over said eighth carbon-doped epitaxial region doped n-type, a tenth compressively strained Si1-w-qGewCq epitaxial region over said ninth silicon epitaxial region having a p-type concentration level greater than 1×
1019 atom/cm3,an eleventh region selected from a group consisting of single crystalline silicon, poly silicon and poly SiGe over said tenth Si1-w-qGewCq region having a p-type concentration level greater than 1×
1019 atoms/cm3,a second vertical structure comprising at least one sidewall extending from said seventh p-type silicon region, eighth carbon-doped epitaxial region, ninth silicon epitaxial region, tenth compressively strained Si1-w-qGewCq epitaxial region, to said eleventh silicon epitaxial region, a twelfth strained Si1-sGes region over a region of said at least one sidewall of said vertical structure, a second gate dielectric region over said twelfth strained Si1-sGes region, and a second gate conducting region over said gate dielectric region. - View Dependent Claims (78, 79, 80, 81, 82)
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83. An inverter comprising:
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a first relaxed Si1-iGei epitaxial region on a first single crystalline substrate, said first Si1-iGei epitaxial layer doped n-type to a concentration level greater than 1×
1019 atoms/cm3,a second tensile strained silicon epitaxial region over said first p-type Si1-iGei region, said second silicon epitaxial region doped n-type to a concentration level greater than 1×
1019 atoms/cm3,a third relaxed Si1-iGei epitaxial region over said second silicon region, said third silicon epitaxial region doped p-type, a fourth tensile strained silicon epitaxial region over said third p-type Si1-iGei region, said fourth strained silicon region doped n-type to a concentration level greater than 1×
1019 atoms/cm3,a fifth region selected from a group consisting of relaxed Si1-iGei, poly silicon and poly SiGe over said fourth n-type strained silicon region, said fifth Si1-iGei region doped n-type to a concentration level greater than 1×
1019 atoms/cm3,a first vertical structure comprising at least one sidewall extending from said first relaxed SiGe region, over said second strained silicon epitaxial region, over said third p-type relaxed Si1-iGei epitaxial region, over said fourth strained silicon epitaxial region to said fifth region, a sixth strained silicon region over a region of said at least one sidewall of said first vertical structure, a first gate dielectric region over said sixth silicon region, and a first gate conducting region over said gate dielectric region, a seventh p-type silicon epitaxial region on a first single crystalline substrate having a concentration level greater than 1×
1019 atoms/cm3,an eighth carbon-doped epitaxial region over said seventh p-type silicon epitaxial region having a p-type to a concentration level greater than 1×
1019 atoms/cm3,a ninth silicon epitaxial region over said eighth carbon-doped epitaxial region doped n-type, a tenth compressively strained Si1-w-qGewCq epitaxial region over said ninth silicon epitaxial region having a p-type concentration level greater than 1×
1019 atoms/cm3,an eleventh region selected from a group consisting of single crystalline silicon, poly Si and poly SiGe over said tenth Si1-w-qGewCq region having a p-type concentration level greater than 1×
1019 atoms/cm3,a second vertical structure comprising at least one sidewall extending from said seventh p-type silicon epitaxial region, eighth carbon-doped epitaxial region, ninth silicon epitaxial region, tenth compressively strained Si1-w-qGewCq epitaxial region, to said eleventh silicon epitaxial region, a twelfth strained Si1-sGes region over a region of said at least one sidewall of said second vertical structure, a second gate dielectric region over said twelfth silicon region, and a second gate conducting region over said gate dielectric region. - View Dependent Claims (84, 85, 86, 87, 88)
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Specification