×

Low leakage heterojunction vertical transistors and high performance devices thereof

  • US 20040256639A1
  • Filed: 06/17/2003
  • Published: 12/23/2004
  • Est. Priority Date: 06/17/2003
  • Status: Active Grant
First Claim
Patent Images

1. A method of preparing a vertical channel of a field effect transistor comprising the steps of:

  • providing a first p-type single crystalline silicon region with a concentration level greater than 1×

    1019 atoms/cm3 on a first substrate, forming a second carbon-doped epitaxial region over said first p-type silicon region, doping said second carbon-doped epitaxial region p-type to a concentration level greater than 1×

    1019 atoms/cm3, forming a third silicon region over said second carbon-doped epitaxial region, doping said third silicon region n-type, forming a fourth compressively strained Si1-w-qGewCq epitaxial region over said third silicon region, doping said fourth compressively strained Si1-w-qGewCq region p-type to a concentration level greater than 1×

    1019 atoM/cm3, forming a fifth silicon epitaxial region over said fourth compressively strained Si1-w-qGewCq region, doping said fifth silicon epitaxial region p-type to a concentration level greater than 1×

    1019 atoms/cm3, forming a vertical structure comprising at least one sidewall extending from said first p-type silicon region, second carbon-doped region, third region of silicon, fourth region of Si1-w-qGewCq epitaxial region, and fifth region of silicon, forming a sixth compressively strained Si1-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region of carbon-doped layer, over said third region of silicon to said fourth compressively strained Si1-w-qGewCq epitaxial region.

View all claims
  • 3 Assignments
Timeline View
Assignment View
    ×
    ×