Semiconductor device and manufacturing method therefor, portable electronic equipment, and IC card

• US 20040256653A1
• Filed: 05/11/2004
• Published: 12/23/2004
• Est. Priority Date: 05/13/2003
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Shibata, Akihide, Ogura, Takayuki, Iwata, Hiroshi
• Granted Patent: US 7,301,198 B2
• Time in Patent Office: Days
• US Class Current: 257/300
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 51/30 characterised by the memory core region
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor switching element and a semiconductor storage element each have a gate electrode, a pair of source/drain regions and a channel forming region. Memory function bodies having a function of storing electric charges are provided on opposite sides of the gate electrode of the semiconductor storage element. In the semiconductor storage element, an amount of current that flows from one of the source/drain regions to the other of the source/drain regions upon application of a voltage to the gate electrode is variable depending on an amount of electric charges retained in the memory function body.

Claims

1. A semiconductor device wherein a logic circuit area having a semiconductor switching element and a memory area having a semiconductor storage element are disposed on one semiconductor substrate;

wherein each of the semiconductor switching element and the semiconductor storage element has a gate electrode, a pair of source/drain regions of first conductivity type formed on portions of a semiconductor substrate surface corresponding to opposite sides of the gate electrode, and a channel forming region of second conductivity type formed between the source/drain regions;

wherein memory function bodies having a function of storing electric charges are provided on the opposite sides of the gate electrode of the semiconductor storage element; and

wherein in the semiconductor storage element, an amount of current that flows from one of the source/drain regions to the other of the source/drain regions upon application of a voltage to the gate electrode is variable depending on an amount of electric charges retained in the memory function body.

2. The semiconductor device as claimed in claim 1, wherein

in the semiconductor switching element, the source/drain regions extend under and overlap with the gate electrode with respect to a channel direction;

and

in the semiconductor storage element, spacings are provided between the gate electrode and each of the source/drain regions with respect to the channel direction, and the memory function bodies having the function of storing electric charges are disposed on the opposite sides of the gate electrode so as to overlap with the spacings at the semiconductor substrate surface, respectively.

3. The semiconductor device as claimed in claim 1, wherein

memory function bodies identical to the memory function bodies of the semiconductor storage element are provided on the opposite sides of the gate electrode of the semiconductor switching element.

4. The semiconductor device as claimed in claim 2, wherein

memory function bodies identical to the memory function bodies of the semiconductor storage element are provided on the opposite sides of the gate electrode of the semiconductor switching element.

5. The semiconductor device as claimed in claim 1, wherein

the memory function bodies are side wall spacers provided on side faces of the gate electrode.

6. The semiconductor device as claimed in claim 2, wherein

the memory function bodies are side wall spacers provided on side faces of the gate electrode.

7. The semiconductor device as claimed in claim 1, wherein

the memory function body comprises a charge retaining portion made of a material having a function of storing electric charges, and an anti-dissipation insulator having a function of preventing dissipation of stored charges;

and

the anti-dissipation insulator has a first insulator that is disposed between the charge retaining portion and the gate electrode and between the charge retaining portion and the semiconductor substrate.

8. The semiconductor device as claimed in claim 2, wherein

the memory function body comprises a charge retaining portion made of a material having a function of storing electric charges, and an anti-dissipation insulator having a function of preventing dissipation of stored charges;

and

the anti-dissipation insulator has a first insulator that is disposed between the charge retaining portion and the gate electrode and between the charge retaining portion and the semiconductor substrate.

9. The semiconductor device as claimed in claim 7, wherein

the anti-dissipation insulator further has a second insulator which is associated with the first insulator to sandwich the charge retaining portion.

10. The semiconductor device as claimed in claim 8, wherein

the anti-dissipation insulator further has a second insulator which is associated with the first insulator to sandwich the charge retaining portion.

11. The semiconductor device as claimed in claim 7, wherein

a topmost position of the charge retaining portion is below a topmost position of the gate electrode.

12. The semiconductor device as claimed in claim 8, wherein

a topmost position of the charge retaining portion is below a topmost position of the gate electrode.

13. The semiconductor device as claimed in claim 7, wherein

a topmost position of the charge retaining portion is below a topmost position of the first insulator.

14. The semiconductor device as claimed in claim 8, wherein

a topmost position of the charge retaining portion is below a topmost position of the first insulator.

15. The semiconductor device as claimed in claim 7, wherein

the charge retaining portion comprises a plurality of fine particles having a function of storing electric charge.

16. The semiconductor device as claimed in claim 8, wherein

the charge retaining portion comprises a plurality of fine particles having a function of storing electric charge.

17. The semiconductor device as claimed in claim 2, wherein

portions of the source/drain regions of the semiconductor switching element that extend under the gate electrode are lower in dopant concentration than other portions of the source/drain regions that are located outside the gate electrode and the memory function bodies.

18. The semiconductor device as claimed in claim 7, wherein

in the semiconductor storage element, at least part of the charge retaining portion overlaps with part of the associated source/drain region.

19. The semiconductor device as claimed in claim 8, wherein

in the semiconductor storage element, at least part of the charge retaining portion overlaps with part of the associated source/drain region.

20. The semiconductor device as claimed in claim 7, wherein

the charge retaining portion has a surface generally parallel to a surface of a gate insulator formed just under the gate electrode.

21. The semiconductor device as claimed in claim 8, wherein

the charge retaining portion has a surface generally parallel to a surface of a gate insulator formed just under the gate electrode.

22. The semiconductor device as claimed in claim 7, wherein

the charge retaining portion has a surface generally parallel to a side face of the gate electrode.

23. The semiconductor device as claimed in claim 8, wherein

the charge retaining portion has a surface generally parallel to a side face of the gate electrode.

24. The semiconductor device as claimed in claim 7, wherein

a film thickness of the first insulator is thinner than a film thickness of a gate insulator formed just under the gate electrode but not less than 0.8 nm.

25. The semiconductor device as claimed in claim 8, wherein

a film thickness of the first insulator is thinner than a film thickness of a gate insulator formed just under the gate electrode but not less than 0.8 nm.

26. The semiconductor device as claimed in claim 7, wherein

a film thickness of the first insulator is thicker than a film thickness of a gate insulator formed just under the gate electrode but not more than 20 nm.

27. The semiconductor device as claimed in claim 8, wherein

a film thickness of the first insulator is thicker than a film thickness of a gate insulator formed just under the gate electrode but not more than 20 nm.

28. An IC card having the semiconductor device as defined in claim 1.

29. An IC card having the semiconductor device as defined in claim 2.

30. Portable electronic equipment having the semiconductor device as defined in claim 1.

31. Portable electronic equipment having the semiconductor device as defined in claim 2.

32. A semiconductor device manufacturing method for forming a semiconductor storage element in a memory area set on a semiconductor substrate while concurrently forming a semiconductor switching element in a logic circuit area set on the semiconductor substrate, comprising:

forming gate electrodes on portions of a semiconductor substrate surface corresponding to the logic circuit area and the memory area, respectively, with a gate insulator disposed between each gate electrode and the semiconductor substrate surface;

in a state that a mask is provided so as to prevent a dopant from being introduced into the memory area, introducing the dopant into the logic circuit area with the gate electrode used as a mask to form a first doped region in the logic circuit area, the first doped region becoming part of a source/drain region;

forming a memory function body having a function of storing electric charges on a side face of the gate electrode in at least the memory area; and

introducing a dopant of a conductivity type identical to that of the dopant used in the foregoing step into the logic circuit area and the memory area with the gate electrodes and the memory function body used as masks to form second doped regions in the logic circuit area and the memory area, the second doped regions becoming at least part of each of source/drain regions in the logic circuit area and the memory area.

33. The semiconductor device manufacturing method as claimed in claim 32, wherein

dopant concentration of the first doped region is lower than dopant concentration of the second doped region.