[FLASH MEMORY CELL STRUCTURE AND METHOD OF MANUFACTURING AND OPERATING THE MEMORY CELL]

• US 20040256657A1
• Filed: 06/20/2003
• Published: 12/23/2004
• Est. Priority Date: 06/20/2003
• Status: Abandoned Application

• Current Assignee: Powerchip Semiconductor Corporation (Powerchip Technology Corporation)
• Original Assignee: Powerchip Semiconductor Corporation (Powerchip Technology Corporation)
• Inventors: HUNG, CHIH-WEI, HUANG, MIN-SAN, HSU, CHENG-YUAN, WU, CHI-SHAN
• Application Number:
  US10/250,286
• Publication Number:
  US 20040256657A1
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A flash memory cell structure is provided. The flash memory cell includes a substrate, a gate structure, a source region, an erase gate, an erase gate dielectric layer, a select gate, a select gate dielectric layer and a drain region. The gate structure is set up over the substrate. The gate structure includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a spacer. The source region is formed in the substrate on one side of the gate structure. The erase gate is formed over the source region on one side of the gate structure. The erase gate dielectric layer is formed between the erase gate and the source region. The select gate is set up on another side of the gate structure. The select gate dielectric layer is formed between the select gate and the substrate. The drain region is formed in the substrate on one side of the select gate.

Claims

1. A flash memory cell, comprising:

a substrate;

a tunneling dielectric layer formed over the substrate;

a floating gate formed over the tunneling dielectric layer;

an inter-gate dielectric layer formed over the floating gate;

a control gate formed over the inter-gate dielectric layer;

a first spacer layer formed on the sidewalls and the top section of the control gate;

a pair of second spacers formed on the sidewalls of the floating gate;

a source region formed in the substrate on a first side of the control gate and the floating gate;

an erase gate formed on the source region;

an erase gate dielectric layer formed between the source region and the erase gate;

a select gate formed on a second side of the control gate and the floating gate;

a select gate dielectric layer formed between the substrate and the select gate; and

a drain region formed in the substrate on one side of the select gate.

2. The flash memory cell of claim 1, wherein the erase gate dielectric layer has a thickness between about 200Ã

□

to 250Ã

□

.

3. The flash memory cell of claim 1, wherein the select gate dielectric layer has a thickness between about 50Ã

□

to 75Ã

□

.

4. The flash memory cell of claim 1, wherein the tunneling dielectric layer has a thickness between about 85Ã

□

to 110Ã

□

.

5. The flash memory cell of claim 1, wherein the cell further comprises a third spacer formed between the select gate and the control gate as well as between the select gate and the floating gate.

6. A flash memory cell, comprising:

a substrate;

a first gate structure and a second gate structure formed on the substrate, wherein the first gate structure and the second gate structure each has at least a floating gate formed over the substrate and a control gate formed over the floating gate;

a source region formed in the substrate between the first gate structure and the second gate structure;

an erase gate formed above the source region between the first gate structure and the second gate structure;

an erase gate dielectric layer formed between the source region and the erase gate;

a first select gate and a second select gate formed on one side of the sidewall of the first gate structure and the second gate structure away from the source region;

a select gate dielectric layer formed between the substrate and the first and second select gate; and

a pair of drain regions formed in the substrate just outside the first select gate and the second select gate.

7. The flash memory cell of claim 6, wherein the erase gate dielectric layer has a thickness between about 200Ã

□

to 250Ã

□

.

8. The flash memory cell of claim 6, wherein the select gate dielectric layer has a thickness between about 50Ã

□

to 75Ã

□

.

9. The flash memory cell of claim 6, wherein each of the first gate structure and the second gate structure further comprises:

a tunneling dielectric layer formed between the floating gate and the substrate;

an inter-gate dielectric layer formed between the control gate and the floating gate;

a first spacer layer formed on the sidewalls and the top section of the control gate; and

a pair of second spacers formed on the sidewalls of the floating gate.

10. The flash memory cell of claim 9, wherein the tunneling dielectric layer has a thickness between about 85Ã

□

to 110Ã

□

.

11. A method of fabricating flash memory cells, comprising the steps of:

providing a substrate, wherein the substrate has a first gate structure and a second gate structure thereon, the first gate structure and the second gate structure each comprises a tunneling dielectric layer formed over the substrate, a floating gate formed over the tunneling dielectric layer, an inter-gate dielectric layer formed over the floating gate, a control gate formed over the inter-gate dielectric layer and a first spacer formed on the sidewalls and the top section of the control gate;

forming a source region in the substrate between the first gate structure and the second gate structure;

forming an erase gate dielectric layer over the upper surface of the source region and forming a second spacer on the sidewalls of the floating gate;

forming an erase gate over the source region such that the erase gate completely fills the space between the first gate structure and the second gate structure;

forming third spacers on the other sides of the first gate structure and the second gate structure corresponding the erase gate;

forming a select gate dielectric layer over the substrate;

forming a first select gate and a second select gate on the sidewall of the third spacers; and

forming a first drain region and a second drain region in the substrate just outside the first select gate and the second select gate.

12. The method of claim 11, wherein the step of forming the first gate structure and the second gate structure furthermore includes:

forming a first dielectric layer over the substrate;

forming a first conductive layer over the dielectric layer;

forming a second dielectric layer over the first conductive layer;

forming a second conductive layer over the second dielectric layer;

patterning the second conductive layer to form the control gate;

forming the first spacer layer on the sidewalls and the top section of the control gate; and

patterning the second dielectric layer, the first conductive layer, the first dielectric layer to form the inter-gate dielectric layer, the floating gate and the tunneling dielectric layer using the first spacer layer and the control gate as a mask.

13. The method of claim 11, wherein the step of forming the erase gate dielectric layer over the source region and a pair of second spacers on the sidewalls of the floating gate includes performing a thermal oxidation process.

14. The method of claim 11, wherein the erase gate dielectric layer has a thickness between about 200Ã

□

to 250Ã

□

.

15. The method of claim 11, wherein the select gate dielectric layer has a thickness between about 50Ã

□

to 75Ã

□

.

16. The method of claim 11, wherein the tunneling dielectric layer has a thickness between about 85Ã

□

to 110Ã

□

.

17. The method of claim 11, wherein the step of forming the select gate dielectric layer over the substrate further comprises a step of forming an insulating layer over the erase gate.

18. The method of claim 17, wherein the step of forming the select gate dielectric layer over the substrate comprises performing a thermal oxidation process.

19. The method of claim 11, wherein the floating gate includes arsenic doped polysilicon layer.

20. A method of operating a flash memory cell, wherein the flash memory cell comprises a substrate, a floating gate formed over the substrate, a control gate formed over the floating gate, a source region formed in the substrate on a first side of the control gate and the floating gate, an erase gate formed above the source region on the firs side of the control gate and the floating gate, a select gate formed on a second side of the sidewall of the control gate and the floating gate, a drain region formed in the substrate just outside the select gate, the operating method comprising the steps of:

applying a first positive voltage to the control gate, applying a second positive voltage to the select gate, applying a third positive voltage to the source region and connecting the drain region to ground so that channel hot electrons are injected to program data into the flash memory cell; and

applying a fourth positive voltage to the erase gate, setting the control gate to 0V and setting the source region and the drain region to a floating state so that the Fowler-Nordheim effect is triggered to erase data from the flash memory cell.