Method for fabricating a vertical transistor in a trench, and vertical transistor

• US 20040256665A1
• Filed: 08/09/2004
• Published: 12/23/2004
• Est. Priority Date: 07/26/2001
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Birner, Albert, Luetzen, Joern
• Granted Patent: US 7,208,370 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

To fabricate a vertical transistor, a trench is provided, the side wall of which is formed by a semiconductor substrate in single crystal form and the base of which is formed by a polycrystalline semiconductor substrate. A transition region is arranged between the side wall and the base. A semiconductor layer is deposited so that an epitaxial semiconductor layer grows on the side wall and a semiconductor layer grows on the base, with a space remaining between these layers. The semiconductor layers are covered with a thin dielectric, which partially limits a flow of current, and the space is filled. During a subsequent heat treatment, dopants diffuse out of the conductive material into the epitaxial semiconductor layer, where they form a doping region. The thin dielectric limits the diffusion of the dopants into the semiconductor substrate and prevents the propagation of crystal lattice defects into the epitaxial semiconductor layer.

Claims

1. A method for fabricating a vertical transistor in a trench, comprising:

providing a trench,

having a base and at least one side wall which consists, at least in certain regions, of a semiconductor material, and

a transition region comprising an insulating material between the regions of the base and the side wall which consist of semiconductor material;

selectively depositing the semiconductor material on the regions of the side wall and the base of the trench which consist of semiconductor material, to form semiconductor layers, during which

at least the semiconductor layer which is deposited on the side wall grows as an epitaxial semiconductor layer, and

a space remains between the semiconductor layers which have been deposited on the base and the side wall;

forming a thin dielectrics, which partially limits an electric current, on at least one of the two semiconductor layers which have been deposited;

filling the space between the two semiconductor layers which have been deposited with a conductive material; and

forming a gate dielectric and a gate electrode on the epitaxial semiconductor layer which has grown.

2. The method as claimed in claim 1, wherein the thin dielectric is substantially limited to 2-3 monolayers.

3. The method as claimed in claim 1, the thin dielectric is formed with a thickness of approximately 5 Å

.

4. The method as claimed in claim 1, wherein the thin dielectric consists of silicon nitride and the deposited semiconductor layers consist of silicon, and the thin dielectric is produced by thermal nitriding of at least one of the two semiconductor layers.

5. The method as claimed in claim 1, wherein the semiconductor material which has been deposited on the base of the trench forms a polycrystalline semiconductor layer.

6. The method as claimed in claim 1, wherein

the thin dielectric is formed on both deposited semiconductor layers, and

before the space is filled with the conductive material, an insulating layer is deposited using a predominantly anisotropic deposition process and is then etched isotropically, so that the insulating layer is removed from vertical surfaces and substantially remains at the base of the trench.

7. The method as claimed in claim 1, wherein

to fill the space with the conductive material trench is substantially filled with the conductive material,

a mask is formed in a region of the trench opening, above the epitaxial semiconductor layer which has been applied to the side wall,

an anisotropic etch is carried out using the mask, during which etch the conductive material is removed from the trench down as far as the space and, a surface of the epitaxial semiconductor layer which faces toward the interior of the trench is uncovered, and

the gate dielectric is formed on the uncovered surface of the epitaxial semiconductor layer.

8. The method as claimed in claim 6, wherein

the anisotropic etching stops at the insulating layer which has remained at the base of the trench,

the insulating layer and the thin dielectric are removed from the base of the trench, and

the cavity which has formed between the conductive material and the semiconductor layer which has been deposited at the base of the trench is filled with a further conductive material.

9. The method as claimed in claim 8, characterized in that the further conductive material (54) is highly doped polysilicon or tungsten silicide.

10. The method as claimed in claim 1, wherein

the conductive material and the semiconductor material, which forms the base of the trench at least in certain regions, are in each case a doped polycrystalline semiconductor material of the first conductivity type;

the semiconductor material which forms at least one side wall at least in certain regions is a semiconductor material of the second conductivity type in single-crystal form; and

the deposited semiconductor layers each have the same conductivity type as the substrate to which they have been applied.

11. The method as claimed in claim 10, wherein a heat treatment is carried out, during which dopants diffuse out of the conductive material into the epitaxial semiconductor layer through the thin dielectric which has been formed on the epitaxial semiconductor layer and in the epitaxial semiconductor layer produce a doping region of the first conductivity type.

12. The method as claimed in claim 1, wherein the trench is an upper part of a capacitor trench, and the semiconductor material located at the base of the trench is formed by the polycrystalline semiconductor material of the inner capacitor electrode of the capacitor.

13. The method as claimed in claim 12, wherein the transition region is formed from the insulating material of an insulation collar of the capacitor trench.

14. The method as claimed in claim 1, wherein the trench has a cross section whose extent is greater than the minimum feature size which can be achieved by lithography.

15. The method as claimed in claim 1, wherein the epitaxial semiconductor layer is doped in situ during its deposition.

16. A method for fabricating a vertical transistor in a trench, comprising:

forming a trench in a single-crystal semiconductor material of a second conductivity type, which apart from its upper part is lined with a dielectric and which is filled with a doped polycrystalline semiconductor material of a first conductivity type, so that an upper partial trench remains, extending above the polycrystalline semiconductor material, a transition region comprising insulating material, which runs approximately in a shape of a ring at a base of the partial trench, being arranged between the polycrystalline semiconductor material located at the base of the partial trench and the single-crystal semiconductor material which forms side walls of the partial trench;

selectively depositing semiconductor material on the side wall and the base of the partial trench, to form semiconductor layers, during which

the semiconductor layer which has been deposited on the side wall grows as an epitaxial semiconductor layer, and

the semiconductor layer which has been deposited on the base grows as a polycrystalline semiconductor layer, and

a space remains between the two semiconductor layers which have been deposited;

forming a thin dielectric, which partially limits an electric current, on the epitaxial semiconductor layer;

filling the space between the two semiconductor layers which have been deposited with a doped polycrystalline semiconductor material of the first conductivity type;

forming a gate dielectric and a gate electrode on the epitaxial semiconductor layer; and

carrying out a heat treatment, as a result of which dopants of the first conductivity type diffuse out of the polycrystalline semiconductor material which has been deposited, through the thin dielectrics, into the epitaxial semiconductor layer where they form a doping region of the first conductivity type.

17. A vertical transistor in a trench, comprising:

at least one side wall and a base, a channel region of the vertical transistor being formed in an epitaxial semiconductor layer which has been deposited on the side wall, and the epitaxial semiconductor layer being connected in an electrically conductive manner to a semiconductor material which forms the base of the trench, wherein a thin dielectric, which partially limits an electric current, is arranged between the epitaxial semiconductor layer and the electrically conductive material.

18. The vertical transistor as claimed in claim 17, wherein the thin dielectric is substantially limited to 2-3 monolayers.

19. The vertical transistor as claimed in claim 17, wherein the thin dielectrics is approximately 5 Å

thick.

20. The vertical transistor as claimed in claim 17 wherein the trench is an upper partial trench of a capacitor trench with an inner capacitor electrodes arranged therein, which electrode is connected to the epitaxial semiconductor layer in an electrically conductive manner via the electrically conductive material.

21. The vertical transistor as claimed in claim 20, wherein the side wall of the trench forms a continuous surface around, and at least the epitaxial semiconductor layer is formed along the surface in a form of two half-shells which lie opposite one another.

22. The vertical transistor as claimed in claim 17, wherein the trench has a cross section whose extent is greater than the minimum feature size which can be achieved by lithography.

23. A semiconductor product having at least one memory cell, comprising:

a trench, which is formed in a semiconductor substrate and has an upper and a lower section;

a storage dielectric which lines at least the lower section of the trench

a capacitor electrode arranged in a lower section of the trench, another capacitor electrode being formed by the semiconductor substrate; and

a vertical transistor formed in the upper section of the trench, wherein

the side wall is formed by the semiconductor substrate, and a base is formed by the capacitor electrodes arranged in the lower section.