Single event hardening of null convention logic circuits
First Claim
1. A system for hardening an asynchronous logic circuit against single event upset, comprising in combination:
- an asynchronous logic circuit including a feedback loop; and
a resistive element placed in the feedback loop operable to create a time constant, wherein the time constant slows feedback response of the feedback loop, thereby allowing transient disturbances to subside prior to being latched by the asynchronous logic circuit.
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Accused Products
Abstract
A system and method for hardening a Null Convention Logic (NCL) circuit against Single Event Upset (SEU) is presented. Placing a resistive element into a feedback loop of the NCL circuit may harden the NCL circuit. A bypass element may be placed in parallel with the resistive element to increase the latching speed of the hardened NCL circuit. Additionally, replacing transistors in an input driver, the feedback loop, and an inverter with transistor stacks, which may include two or more transistors connected in series, may harden the NCL circuit. Further, two NCL gates may be cross-coupled to harden the NCL circuit.
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Citations
28 Claims
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1. A system for hardening an asynchronous logic circuit against single event upset, comprising in combination:
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an asynchronous logic circuit including a feedback loop; and
a resistive element placed in the feedback loop operable to create a time constant, wherein the time constant slows feedback response of the feedback loop, thereby allowing transient disturbances to subside prior to being latched by the asynchronous logic circuit. - View Dependent Claims (2, 3, 4, 5)
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- 6. A method for hardening an asynchronous logic circuit against single event upset, comprising connecting a resistive element in a feedback loop of the asynchronous logic circuit, wherein the resistive element creates a time constant operable to slow feedback response of the feedback circuit, thereby allowing transient disturbances to subside prior to being latched by the asynchronous logic circuit.
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11. A system for hardening an asynchronous logic circuit against single event upset, comprising in combination:
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an input driver for receiving inputs to the asynchronous logic circuit;
a feedback loop;
an inverter located within the feedback loop; and
at least one transistor stack located in at least one of the input driver, the feedback loop, and the inverter, wherein the at least one transistor stack is operable to prevent energetic particles from turning on all transistors in the at least one transistor stack, thereby hardening the asynchronous logic circuit from single event upset. - View Dependent Claims (12, 13, 14)
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- 15. A method for hardening an asynchronous logic circuit against single event upset, comprising placing at least one transistor stack in at least one of an input driver, a feedback loop, and an inverter in the asynchronous logic circuit, wherein the at least one transistor stack is operable to prevent energetic particles from turning on all transistors in the at least one transistor stack.
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19. A system for hardening an asynchronous logic circuit against single event upset, comprising in combination:
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a first asynchronous logic gate; and
a second asynchronous logic gate, wherein an output of the first asynchronous logic gate is connected to an input of a feedback loop in the second asynchronous logic gate and an output of the second asynchronous logic gate is connected to an input of a feedback loop in the first asynchronous logic gate, wherein the asynchronous circuit is operable to reset itself to a correct state after entering an error state. - View Dependent Claims (20, 21, 22, 23, 28)
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24. A method for hardening an asynchronous logic circuit against single event upset, comprising in combination:
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connecting an output of a first asynchronous logic gate to an input of a feedback loop in a second asynchronous logic gate; and
connecting an output of the second asynchronous logic gate to an input of a feedback loop in the first asynchronous logic gate, wherein if the output of the first asynchronous logic gate and the output of the second asynchronous logic gate are at a level representing DATA then the asynchronous logic circuit enters an error state, wherein the asynchronous logic circuit resets itself to a correct state after entering the error state. - View Dependent Claims (25, 26, 27)
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Specification