Semiconductor integrated circuit

• US 20040257133A1
• Filed: 04/29/2004
• Published: 12/23/2004
• Est. Priority Date: 05/26/2003
• Status: Abandoned Application

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Ishikawa, Atsushi
• Application Number:
  US10/834,169
• Publication Number:
  US 20040257133A1
• Time in Patent Office: Days
• US Class Current: 327/172
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68

Abstract

The invention provides a semiconductor integrated circuit incorporating a clock signal multiplying circuit which can generate a double multiplied clock signal in following up changes in power voltage and a frequency of a reference clock signal without using a phase comparator. The semiconductor integrated circuit can include first circuits which delay clock signals in stages, a second circuit which selects one of a plurality of delay clock signals which have been provided with different delays in the first circuits, and a third circuit which generates a double multiplied clock signal with a frequency double the clock signal based on a delay clock signal selected by the clock signals inputted to the first circuits and the second circuit.

Claims

1. A semiconductor integrated circuit, comprising:

a first circuit that delays a clock signal in stages;

a second circuit that selects one from a plurality of delay clock signals being provided with different delays in the first circuit; and

a third circuit that generates a double multiplied clock signal of which a frequency is doubled from of a frequency of the clock signal, based on a clock signal inputted to the first circuit and the delay clock signal selected by the second circuit.

2. 3The semiconductor integrated circuit according to claim 1, the first circuit further including a plurality of buffers coupled in series.

3. The semiconductor integrated circuit according to claim 1, the third circuit further including a circuit that generates the double multiplied clock signal of which a frequency is doubled from the frequency of the clock signal by obtaining an exclusive OR of the clock signal inputted to the first circuit and the delay clock signal selected by the second circuit.

4. The semiconductor integrated circuit according to claim 3, further comprising:

a control circuit that controls the second circuit based on a duty of the double multiplied clock signal generated by the third circuit.

5. The semiconductor integrated circuit according to claim 4, the control circuit further including:

a low-pass filter that integrates the double multiplied clock signal generated by the third circuit; and

a comparator or an AD converter that compares an output voltage of a low-pass filter with a reference voltage and outputs a comparative result obtained thereby as a control signal.

6. The semiconductor integrated circuit according to claim 5, the second circuit including a circuit that selects one of a plurality of delay clock signals respectively outputted by a prescribed buffer of the plurality of buffers in accordance with a control signal outputted by the control circuit.