Memory module and memory system

• US 20040257847A1
• Filed: 04/21/2004
• Published: 12/23/2004
• Est. Priority Date: 04/21/2003
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Ikeda, Hiroaki, Matsui, Yoshinori, Sugano, Toshio
• Granted Patent: US 7,123,497 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, it has become clear that there is a restriction on the transfer rate of the system data signal and that speeding-up cannot be expected. A current consumption in a plurality of DRAMs constituting the memory module is large, and this is also a factor for hindering the speeding-up. There is obtained a memory module in which a plurality of DRAM chips are stacked on an IO chip and in which each DRAM chip is connected to the IO chip by a through electrode and which comprises a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. In this constitution, a wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Claims

1. A memory module comprising:

a system input/output terminal via which a system data signal having a predetermined data width is input/output; and

a plurality of memory chips which transmit/receive an internal data signal broader than the system input/output terminal, the memory module further comprising;

an IO chip including a function of performing conversion between the system data signal and the internal data signal in the system input/output terminal, the plurality of memory chips being stacked on the IO chip and being connected to the IO chip via through electrodes extending through the plurality of stacked memory chips.

2. The memory module according to claim 1, further comprising:

an interposer substrate for mounting the IO chip, the interposer substrate having a terminal for mounting, constituting the system input/output terminal.

3. A memory module comprising:

an IO chip;

a plurality of DRAMs stacked on the IO chip; and

an interposer substrate having BGA terminals of all system data signals, system address signals, system control signals, and system clock signals required to constitute a function of a memory sub-system of one channel, and including a constitution in which a plurality of DRAM chips connected to a pad for input/output and a pad for input of each input/output circuit on the IO chip and stacked on the IO chip are bonded to a data signal terminal, an address signal terminal, and a control signal terminal of the IO chip by the through electrodes, a data signal, an address signal, and a control signal between the chips are received/transmitted via the through electrodes, and a power supply and GND are supplied to the pads on the IO chip from the BGA terminals, and supplied to a power supply of each DRAM chip and a GND terminal via the through electrode.

4. The memory module according to claim 3, wherein the data signal terminals of the respective DRAMs share a data signal line via the through electrodes and are connected to the data signal terminal of the IO chip, the address signal terminals of the respective DRAMs share an address signal line via the through electrodes and are connected to the address signal terminal of the IO chip, and the control signal terminals of the respective DRAMs share a control signal line via the through electrodes and are connected to the control signal terminal of the IO chip.

5. The memory module according to claim 3, wherein the DRAM chip has the number, which is 2n (n denotes a natural number of 1 or more) times that of system data buses, of through electrode data signal terminals for write and read, or bidirectional terminals, and the IO chip further has the number, which is 2n times that of system data buses, of through electrode data signal terminals for write and read, or bidirectional terminals.

6. The memory module according to claim 3, wherein the DRAM chip and the IO chip mutually transfer data via a through electrode data terminal, whereas the IO chip has a serial/parallel circuit which serial/parallel converts 2n data signals per continuous terminal transferred via a system data bus to simultaneously transfer the data signals to the DRAM chip, and a parallel/serial circuit which parallel/serial converts 2n data signals per terminal transferred from the DRAM chip to output continuous 2n data to the system data bus.

7. The memory module according to claim 3, wherein SPD chips are stacked on the stacked DRAM chips.

8. The memory module according to claim 7, wherein an input/output signal terminal of the SPD chip is connected to an SPD input/output terminal pad on the IO chip via the through electrode, and each DRAM chip has a through electrode for an SPD input/output signal, which is not used in the DRAM chip.

9. The memory module according to claim 3, wherein a pattern other than a pattern for forming the through electrode is formed using the same pattern for the DRAM chips to be stacked.

10. The memory module according to claim 3, wherein the same pattern is formed for all of the DRAM chips to be stacked, and a fuse data is cut to identify signals for the individual DRAM chips from the IO chip.

11. A memory module comprising:

an IO chip;

a plurality of DRAM chips stacked on the IO chip; and

an interposer substrate having BGA terminals of all system data signals, system address signals, system control signals, and system clock signals required to constitute a function of a memory sub-system of one channel, wherein each DRAM chip comprises a counter circuit which generates a collation signal with which a control signal or an address signal transmitted from the IO chip is collated to receive a signal, and has a constitution in which the DRAM chips having at least two types of different through electrode forming patterns are alternately stacked.

12. The memory module according to claim 11, wherein a plurality of bit signals outputted from the IO chip are input into the counter circuit on the DRAM chip of a lowermost layer, an output is input into the counter circuit on the DRAM chip of the next layer, the output is input into the counter circuit on the DRAM chip of the next layer, and a successively incremented signal is accordingly transmitted to the DRAM chip of an uppermost layer so that the respective DRAM chips obtain different counter output values.

13. The memory module according to claim 11, wherein the DRAM chip produces the collation signal in response to a counter output value, collates the collation signal with the control signal or the address signal transmitted from the IO chip, and takes in a signal transmitted from the IO chip in case of agreement.

14. The memory module according to claim 11, wherein the DRAM chip comprises a logic circuit which produces a logic of a laminate number of the DRAM chip for a DRAM chip selection signal transmitted from the IO chip in accordance with a counter output value.

15. The memory module according to claim 14, wherein the logic circuit of each DRAM chip takes in the signal transmitted from the IO chip in a case where a logic value of the DRAM chip selection signal transmitted from the IO chip agrees with the logic.

16. A memory module comprising:

an IO chip;

a plurality of DRAM chips stacked on the IO chip; and

an interposer substrate having BGA terminals of all system data signals, system address signals, system control signals, and system clock signals required to constitute a function of a memory sub-system of one channel, wherein all the DRAM chips to be stacked have the same pattern, comprise a plurality of fuse devices, and produce collation signals indicating stacked positions by cut positions of the fuse device.

17. The memory module according to claim 16, wherein the DRAM chip changes a level of a laminate number recognition signal line shared by each DRAM and IO chip via the through electrode in response to the collation signal.

18. The memory module according to claim 17, wherein the IO chip recognizes the number of DRAMs stacked by the laminate number recognition signal line level, and allocates a logic level of the control signal or the address signal to each DRAM.

19. A memory module comprising:

a system input/output terminal via which a system data signal having a predetermined data width is input/output; and

a plurality of memory chips which transmit/receive an internal data signal broader than the system input/output terminal, the memory module further comprising;

an IO chip including a function of performing conversion between the system data signal and the internal data signal in the system input/output terminal, the plurality of memory chips being stacked on the IO chip and being connected to the IO chip by through electrodes extending through the plurality of stacked memory chips, the respective stacked DRAM chips having a bank constitution and selectively operating by a bank selection signal logically produced from a system bank selection signal by the IO chip.

20. The memory module according to claim 19, wherein each of the stacked DRAM chips collates the bank selection signal logically produced by the IO chip with a collation signal indicating the laminate number of each DRAM chip to produce a DRAM chip activation signal or a latch signal in the DRAM.

21. The memory module according to claim 20, wherein the IO chip has a function of changing the logic of the bank selection signal in accordance with the constitution of the stacked DRAM chip.

22. The memory module according to claim 19, wherein the IO chip changes the logic of the bank selection signal by the laminate number recognition signal indicating the number of laminates of the DRAM chips stacked on the IO chip.

23. The memory module according to claim 22, wherein the IO chip changes the logic of the bank selection signal by a potential level given to the laminate number recognition signal and the BGA terminal.

24. The memory module according to claim 19, wherein the IO chip includes a through electrode terminal for individually receiving/transmitting signals with some of the stacked DRAM chips.

25. The memory module according to claim 19, wherein each of the stacked DRAM chips includes a plurality of through electrode terminals for the IO chip and the individual DRAMs to receive/transmit signals, and a counter circuit connected to the through electrode terminal, and the DRAM chip is selected in accordance with a counter value of the counter circuit.

26. The memory module according to claim 19, wherein each DRAM chip comprises a plurality of fuse circuits comprising fuse devices, and cut the fuse data of each fuse circuit to produce a signal for selecting the stacked DRAM.

27. The memory module according to claim 19, wherein the DRAM chip triggers a signal transmitted from the IO chip via the through electrode to take in another signal transmitted from the IO chip.

28. The memory module according to claim 19, wherein the DRAM chip controls a DRAM Internal circuit by the signal transmitted from the IO chip via the through electrode.

29. A memory module comprising:

an interposer substrate comprising a BGA terminal via which a system data signal is input/output; and

two IO chips mounted on the interposer substrate, each IO chip being connected to ½

of system data signal BGA terminals and comprising a constitution in which BGA terminals other than those of data such as an address, command, and clock are shared, a plurality of DRAM chips being stacked on the two IO chips.

30. The memory module according to claim 29, wherein the DRAM chips stacked on the two IO chips constitute two ranks to be simultaneously accessed.

31. The memory module according to claim 29, an SPD chip is mounted on an uppermost stage of one of the two DRAM chip laminates.

32. A memory module comprising:

a system input/output terminal via which a system data signal having a predetermined data width is input/output; and

a plurality of memory chips which transmit/receive an internal data signal broader than the system input/output terminal, the memory module further comprising;

an IO chip having a function of performing conversion between the system data signal and the internal data signal in the system input/output terminal, the plurality of memory chips being stacked on the IO chip and being connected to the IO chip via through electrodes extending through the plurality of stacked memory chips, a plurality of banks controlled by individual array control circuits being constituted inside each DRAM chip.

33. The memory module according to claim 32, wherein the bank of the DRAM chip is selectively operated in response to a bank selection signal taken in by an activation signal of each DRAM chip, and a bank number of the whole module is obtained by DRAM chip number×

DRAM internal bank.

34. The memory module according to claim 32, wherein a page size at a time when the inside of the DRAM chip is operated as a plurality of banks (n banks) is 1/n.

35. The memory module according to claim 32, wherein the IO chip comprises means for transmitting a bank mode signal for selecting whether or not to operate the inside of each DRAM chip as a plurality of banks (n banks) to the DRAM chip.

36. The memory module according to claim 35, wherein the bank mode signal is transmitted as a terminal level signal from a memory controller.

37. The memory module according to claim 32, further comprising:

a structure in which an SPD chip is mounted on the IO chip via a common electrode and a signal terminal is connected to the interposer substrate via a pad on the IO chip to read a SPD signal in the IO chip.

38. The memory module according to claim 37, wherein information is read also in the IO chip and used in producing a control signal of the DRAM chip, when the information written in SPD is read by a memory controller at a system boot time to automatically set a control condition.

39. The memory module according to claim 37, wherein the IO chip reads setting information such as internal timing setting written in SPD at a manufacturing time and a module constitution to set a read internal circuit to set an internal circuit at an initial setting time of the memory module.

40. A memory module comprising:

a system input/output terminal via which a system data signal having a predetermined data width is input/output; and

a plurality of memory chips which transmit/receive an internal data signal broader than the system input/output terminal, the memory module further comprising;

an IO chip including a function of performing conversion between the system data signal and the internal data signal in the system input/output terminal, the plurality of memory chips being stacked on the IO chip and being connected to the IO chip by through electrodes extending through the plurality of stacked memory chips, each of the stacked DRAM chips comprising a pad for exclusive use in a test and a test circuit connected to the pad for exclusive use in the test.

41. The memory module according to claim 40, wherein a test command, test address, and test data signal are supplied from the pad for exclusive use in the test in synchronization with a test trigger signal at a DRAM chip test time, and an address, command, and data signal produced by the test circuit are received by a latch signal for a test produced by the test circuit to start an internal operation.

42. A memory system comprising:

a plurality of memory modules; and

a memory controller, each of the plurality of memory module comprising a constitution in which an IO chip and a plurality of memory chips stacked on the IO chip are stacked, the IO chips in the plurality of memory modules being connected to the memory controller by a common signal wiring, the IO chip being connected to the memory chip stacked on the IO chip by through electrodes more than the signal wirings.

43. The memory system according to claim 42, wherein the plurality of memory modules are mounted in a plane on a common mother board together with the memory controller via the interposer substrate, and the signal wiring is laid on the mother board.

44. The memory system according to claim 42, wherein the plurality of memory modules are mounted on a common mounting substrate, the mounting substrate is mounted on a mother board together with a memory controller, and the signal wiring is laid on the mother board and the mounting substrate.

45. A memory system comprising:

a plurality of memory chips which transmit/receive a system data signal at a predetermined transfer rate and which transmit/receive an internal data signal at an internal processing rate lower than the transfer rate, the system further comprising;

an IO chip comprising a terminal which transmits/receives a data signal at the predetermined transfer rate and which performs conversion between the internal data signal at the internal processing rate and the system data signal at the transfer rate, the plurality of memory chips being stacked on the IO chip.