Integrated optical/electronic circuits and associated methods of simultaneous generation thereof

• US 20040258348A1
• Filed: 07/13/2004
• Published: 12/23/2004
• Est. Priority Date: 05/17/2001
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Sioptical Inc. (Cisco Systems, Inc.)
• Inventors: Deliwala, Shrenik
• Granted Patent: US 6,895,136 B2
• Time in Patent Office: Days
• US Class Current: 385/14
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: G02B 2006/12038 Glass (SiO2 based materials)
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 2006/12097 Ridge, rib or the like
• CPC Class Codes: G02B 2006/12104 Mirror; Reflectors or the like
• CPC Class Codes: G02B 2006/12107 Grating
• CPC Class Codes: G02B 2006/12114 Prism
• CPC Class Codes: G02B 2006/12135 Temperature control
• CPC Class Codes: G02B 2006/12161 Distributed feedback [DFB]
• CPC Class Codes: G02B 2006/12164 Multiplexing; Demultiplexing
• CPC Class Codes: G02B 2006/12176 Etching
• CPC Class Codes: G02B 27/285 comprising arrays of elements, e.g. microprisms
• CPC Class Codes: G02B 5/045 Prism arrays
• CPC Class Codes: G02B 6/10 of the optical waveguide type G02B6/02, G02B6/24 take precedence; devices or arrangements for the control of light by electric, magnetic, electro-magnetic or acoustic means G02F1/00; transferring the modulation of modulated light G02F2/00; optical logic elements G02F3/00; optical analogue/digital converters G02F7/00
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/12007 forming wavelength selective elements, e.g. multiplexer, demultiplexer
• CPC Class Codes: G02B 6/12011 characterised by the arrayed waveguides, e.g. comprising a filled groove in the array section
• CPC Class Codes: G02B 6/12026 characterised by means for reducing the temperature dependence
• CPC Class Codes: G02B 6/12033 characterised by means for configuring the device, e.g. moveable element for wavelength tuning switching G02B6/35; thermo-optic devices G02F1/0147
• CPC Class Codes: G02B 6/1225 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: G02B 6/1228 : Tapered waveguides, e.g. integrated spot-size transformers for coupling with fibres G02B6/305
• CPC Class Codes: G02B 6/124 : Geodesic lenses or integrated gratings
• CPC Class Codes: G02B 6/2861 : using fibre optic delay lines and optical elements associated with them, e.g. for use in signal processing, e.g. filtering delay lines in general H03H, H01P9/00; optical computing devices G06E
• CPC Class Codes: G02B 6/29349 : Michelson or Michelson/Gires-Tournois configuration, i.e. based on splitting and interferometrically combining relatively delayed signals at a single beamsplitter
• CPC Class Codes: G02B 6/29358 : Multiple beam interferometer external to a light guide, e.g. Fabry-Pérot, etalon, VIPA plate, OTDL plate, continuous interferometer, parallel plate resonator G02B6/29347, G02B6/29349, G02B6/2935, G02B6/29361 take precedence; resonator evanescently coupled to light guide G02B6/29335
• CPC Class Codes: G02B 6/34 : utilising prism or grating G02B6/293 takes precedence
• CPC Class Codes: G02B 6/4215 : the intermediate optical elements being wavelength selective optical elements, e.g. variable wavelength optical modules or wavelength lockers G02B6/4246 takes precedence
• CPC Class Codes: G02B 6/4232 : using the surface tension of fluid solder to align the elements, e.g. solder bump techniques flip-chip mounting techniques in assembly of semiconductor devices H01L24/81
• CPC Class Codes: G02B 6/43 : Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: G02F 1/0147 : based on thermo-optic effects G02F1/132 takes precedence
• CPC Class Codes: G02F 1/0152 : using free carrier effects, e.g. plasma effect
• CPC Class Codes: G02F 1/025 : in an optical waveguide structure G02F1/017, G02F1/2257 take precedence
• CPC Class Codes: G02F 1/295 : Analog deflection from or in an optical waveguide structure]
• CPC Class Codes: G02F 2201/20 : delay line
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A method for forming a hybrid active electronic and optical circuit using a lithography mask. The hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device on a Silicon-On-Insulator (SOI) wafer. The SOI wafer including an insulator layer and an upper silicon layer. The upper silicon layer including at least one component of the active electronic device and at least one component of the optical device. The method comprising projecting the lithography mask onto the SOI waver in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the SOI wafer.

Claims

1-15. -15. cancelled

16. A method for forming a hybrid active electronic and optical circuit using a lithography mask, the hybrid active electronic and optical circuit comprising an active electronic device and at least one active optical device, both devices disposed at least in part in a single Silicon-On-Insulator (SOI) wafer, the SOI wafer including an insulator layer and an upper silicon layer, the upper silicon layer including at least one component of the active electronic and at least one component of the active optical device, the active optical device also comprising a polysilicon region disposed above the upper silicon layer forming a polysilicon loaded region wherein the higher effective mode index of the polysilicon loaded region controls the confinement of the light propagating within the upper silicon layer, the method comprising projecting the lithography mask onto the SOI wafer in order to simultaneously pattern at least a portion of the active electronic device and at least a portion of the at least one active optical device.

17. The method as defined in claim 16 wherein the active optical device includes one from the group of a p-n device, a field plated device, a Schottky device, a MOSCAP device and a MOSFET device.

18. The method as defined in claim 17 wherein the active optical device is a MOSCAP device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the polysilicon region such that the MOSCAP device is defined by the upper silicon layer of the SOI wafer forming the “

Semiconductor”

portion of the MOSCAP device, the relatively thin oxide layer forming the “

Oxide”

portion of the MOSCAP device and the polysilicon region is sufficiently doped to form the “

Metal”

portion of the MOSCAP device.

19. The method as defined in claim 17 wherein the active optical device is a MOSFET device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the polysilicon region such that the MOSFET device is defined by the upper silicon layer of the SOI wafer forming the “

Semiconductor”

portion of the MOSFET device, the relatively thin oxide layer forming the “

Oxide”

portion of the MOSFET device and the polysilicon region is sufficiently doped to form the “

Metal”

portion of the MOSFET device.

20. The method as defined in claim 16 wherein the polysilicon region is positioned and shaped to create a desired position and shape of the optical mode field within the upper silicon layer and the polysilicon region.

21. The method as defined in claim 16 wherein the polysilicon region comprises multiple layers of polysilicon disposed above the upper silicon layer.

22. The method as defined in claim 21 wherein the multiple layer polysilicon region is positioned and shaped to create a desired position and shape of the optical mode field within the upper silicon layer and the multiple layer polysilicon region.

23. The method as defined in claim 21 wherein the active optical device includes one from the group of a p-n device, a field plated device, a Schottky device, a MOSCAP device and a MOSFET device.

24. The method as defined in claim 23 wherein the active optical device is a MOSCAP device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the multiple layer polysilicon region such that the MOSCAP device is defined by the upper silicon layer of the SOI wafer forming the “

Semiconductor”

portion of the MOSCAP device, the relatively thin oxide layer forming the “

Oxide”

portion of the MOSCAP device and at least one layer of the multiple layer polysilicon region is sufficiently doped to form the “

Metal”

portion of the MOSCAP device.

25. The method as defined in claim 23 wherein the active optical device is a MOSCAP device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the multiple layer polysilicon region such that the MOSCAP device is defined by the upper silicon layer of the SOI wafer forming the “

Semiconductor”

portion of the MOSCAP device, the relatively thin oxide layer forming the “

Oxide”

portion of the MOSCAP device and at least one layer of the multiple layer polysilicon region is lightly doped to form a semiconductor layer of the active optical device.

26. A hybrid electronic and optical circuit integrated with a Silicon-On-Insulator (SOI) wafer, the SOI wafer including an insulator layer and an upper silicon layer, the hybrid active electronic and optical circuit comprising:

a relatively thin optical waveguide formed within at least a portion of the upper silicon layer of the SOI wafer; and

at least one active optical device including both a portion of the relatively thin optical waveguide within the upper silicon layer of the SOI wafer and a polysilicon region disposed above the upper silicon layer so as to form a polysilicon loaded region wherein the higher effective mode index of the polysilicon loaded region controls the confinement of the light propagating within the upper silicon layer and wherein altering an electric voltage applied between the polysilicon region and the upper silicon layer affects a free carrier distribution in a portion of the at least one active optical device, thereby changing the effective mode index of the at least one active optical device and altering the optical characteristics of a lightwave signal passing therethrough.

27. The hybrid active electronic and optical circuit as defined in claim 26 wherein the active optical device includes one from the group of a p-n device, a field plated device, a Schottky device, a MOSCAP device and a MOSFET device.

28. The hybrid active electronic and optical circuit as defined in claim 27 wherein the active optical device further includes a relatively thin oxide layer disposed between the upper silicon layer and the polysilicon region such that the MOSCAP device structure is defined by the upper silicon layer of the SOI wafer forming the “

Semiconductor”

portion of the MOSCAP device, the relatively thin oxide layer forming the “

Oxide”

portion of the MOSCAP device and the polysilicon region is sufficiently doped to form the “

Metal”

portion of the MOSCAP device wherein the altering of an electric voltage applied between the polysilicon region and the upper silicon layer affects the distribution of free carriers near the semiconductor/oxide boundary.

29. The hybrid active electronic and optical circuit as defined in claim 26 wherein the polysilicon region is positioned and shaped to create the desired position and shape of the optical mode field within the upper silicon layer and the polysilicon region.

30. The hybrid active electronic and optical circuit as defined in claim 26 wherein the polysilicon region comprises multiple layers of polysilicon disposed above the upper silicon layer.

31. The hybrid active electronic and optical circuit as defined in claim 30 wherein the multiple layer polysilicon region is positioned and shaped to create a desired position and shape of the optical mode field within the upper silicon layer and the multiple layer polysilicon region.

32. The hybrid active electronic and optical circuit as defined in claim 30 wherein the active optical device includes one from the group of a p-n device, a field plated device, a Schottky device, a MOSCAP device and a MOSFET device.

33. The hybrid active electronic and optical circuit as defined in claim 32 wherein the active optical device is a MOSCAP device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the multiple layer polysilicon region such that the MOSCAP device is defined by the upper silicon layer of the SOI wafer forming the “

Semiconductor”

portion of the MOSCAP device, the relatively thin oxide layer forming the “

Oxide”

portion of the MOSCAP device and at least one layer of the multiple layer polysilicon region is sufficiently doped to form the “

Metal”

portion of the MOSCAP device wherein the altering of an electric voltage applied between the polysilicon region and the upper silicon layer affects the distribution of free carriers near the semiconductor/oxide boundary.

34. The hybrid active electronic and optical circuit as defined in claim 32 wherein the active optical device is a MOSCAP device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the multiple layer polysilicon region such that the MOSCAP device is defined by the upper silicon layer of the SOI wafer forming the “

Semiconductor”

portion of the MOSCAP device, the relatively thin oxide layer forming the “

Oxide”

portion of the MOSCAP device and at least one layer of the multiple layer polysilicon region is lightly doped to form a semiconductor layer of the active optical device wherein the altering of an electric voltage applied between the polysilicon region and the upper silicon layer affects the distribution of free carriers near the semiconductor/oxide boundaries.

35. The hybrid active electronic and optical circuit as defined in claim 32 wherein the active optical device is a MOSFET device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the polysilicon region such that the MOSFET device is defined by the upper silicon layer of the SOI wafer forming the “

Semiconductor”

portion of the MOSFET device, the relatively thin oxide layer forming the “

Oxide”

portion of the MOSFET device and the polysilicon region is sufficiently doped to form the “

Metal”

portion of the MOSFET device.