Bit synchronization circuit and central terminal for PON systems

• US 20040258410A1
• Filed: 09/04/2003
• Published: 12/23/2004
• Est. Priority Date: 06/17/2003
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi Communication Technologies, Ltd. (Hitachi, Ltd.)
• Inventors: Kazawa, Tohru, Yajima, Yusuke, Ashi, Toshihiro
• Granted Patent: US 7,239,813 B2
• Time in Patent Office: Days
• US Class Current: 398/71
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data selector for selectively passing optimum phase data train indicated by the control signal, and a data synchronization unit for converting the optimum phase data train to a data train in synchronization with a reference clock. The phase determination unit repeatedly detecting the optimum phase data train during the same burst data set is received. When optimum phase varies, the output data selector dynamically switches the optimum phase data train to be supplied to the data synchronization unit.

Claims

1. A bit synchronization circuit for synchronizing, with an internal reference clock, burst data sets received in time series order, the circuit comprising:

a multiphase data sampling unit for converting each of the received burst data sets to multiphase data trains having phases different from each other;

a phase determination unit for detecting, from among said multiphase data trains, an optimum phase data train having the highest phase margin over the reference clock and generating a control signal indicating the optimum phase data train;

an output data selector for selectively passing, of the multiphase data trains outputted from said data sampling portion, the optimum phase data train indicated by said control signal; and

a data synchronization unit for converting the data train passed through said output data selector to a data train in synchronization with said reference clock and outputting the resulting data train, wherein

said phase determination unit repeatedly performs the operation of detecting said optimum phase data train during a period during which the same burst data set is received and, if an optimum phase varies, said output data selector dynamically switches the optimum phase data to be supplied to said data synchronization unit in response to the control signal outputted from said phase determination unit.

2. The bit synchronization circuit according to claim 1, wherein said phase determination unit has first means for detecting the optimum phase data train in each cycle of said reference clock and second means for cumulatively summing the number of times the optimum phase data train is detected by said first means for each of the different phases and generating, regarding the phase for which the cumulative sum reaches a reference value as the optimum phase, a control signal indicating said optimum phase data train, said second means clearing the number of detections for each of the different phases on every determination of the optimum phase and repeating the cumulative summation of the number of detections for each of the different phases.

3. The bit synchronization circuit according to claim 2, wherein said second means determines a first optimum phase in each of the burst data sets based on a first cumulative reference value and thereafter determines the optimum phase based on a second cumulative reference value different from said first cumulative reference value.

4. The bit synchronization circuit according to claim 3, wherein said second cumulative reference value is adjusted to be larger than said first cumulative reference value.

5. The bit synchronization circuit according to claim 1, further comprising:

means for correcting a disturbance in data continuity occurring in the output data train from said output data selector upon the dynamic switching of said optimum phase data train.

6. The bit synchronization circuit according to claim 1, further comprising:

means for generating a missing data supplying data train from the most-delayed-phase data train outputted from said multiphase data sampling unit and supplying, to said data synchronization unit, said missing data supplying data train in parallel relation with said optimum phase data train, wherein

said phase determination unit has means for detecting a phase variation under a specified condition which disturbs continuity of the optimum phase data and generating a data train correction signal and

said data synchronization unit is provided with data transfer control means for selecting, in response to said data train correction signal, data to be transferred as the output data train from between said optimum phase data train and said missing data supplying data train.

7. The bit synchronization circuit according to claim 6, wherein

said means for generating the data train correction signal detects that the optimum phase has changed from a most delayed phase to a most advanced phase to generate a first control signal as said data train correction signal and detects that the optimum phase has changed from the most advanced phase to the most delayed phase to generate a second control signal as said data train correction signal, and

said data transfer control means deletes, from said optimum phase data train, data supplied upon the generation of said first control signal and performs an operation of selecting said data such that missing data supplying data supplied upon the generation of said second control signal is inserted compensatorily immediately before the optimum phase data supplied upon the generation of said second control signal.

8. The bit synchronization circuit according to claim 7, wherein

said data synchronization unit has a first memory for storing a part of said optimum phase data train, a second memory for storing a part of said missing data supplying data train, and a selector for selectively outputting data read from said first and second memories as said output data train, and

said data transfer control means dynamically controls said selector and writing and reading of data to and from said first and second memories in response to said first and second control signals.

9. A central terminal for an optical transmission system for communicating with a plurality of remoter terminals, said central terminal having at least one subscriber line interface connected to an optical fiber for receiving burst data sets in time series order transmitted from the remoter terminals in time division multiplex, said optical fiber accommodating the plurality of remote terminals via a plurality of tributary optical fibers branched from the optical fiber with an optical coupler,

said subscriber line interface including an optical/electric signal converter for converting an optical signal received from said optical fiber to an electric signal, and a bit synchronization circuit connected to said optical/electric signal converter for synchronizing, with an internal reference clock, burst data sets supplied in an electric signal outputted from said optical/electric signal converter in time series order, said bit synchronization circuit comprising:

a multiphase data sampling unit for converting each of the received burst data sets to multiphase data trains having phases different from each other;

a phase determination unit for detecting, from among said multiphase data trains, an optimum phase data train having the highest phase margin over the reference clock and generating a control signal indicating the optimum phase data train;

an output data selector for selectively passing, of the multiphase data trains outputted from said data sampling portion, the optimum phase data train indicated by said control signal; and

a data synchronization unit for converting the data train passed through said output data selector to a data train in synchronization with said reference clock and outputting the resulting data train, wherein

said phase determination unit repeatedly performs the operation of detecting said optimum phase data train during a period during which the same burst data set is received and, if an optimum phase varies, said output data selector dynamically switches the optimum phase data to be supplied to said data synchronization unit in response to the control signal outputted from said phase determination unit.

10. A central terminal for an optical transmission system according to claim 9, wherein

said optical/electric signal converter has an automatic threshold control (ATC) function of setting a variable threshold for identifying the optical signal for each of received burst data sets, resetting said threshold to an offset value within a no-signal segment generated between the individual burst data sets, and awaiting the optical signal for the subsequent burst data set,

said bit synchronization circuit has means for generating a mask signal for initiating a mask period in response to a threshold reset signal supplied from said optical/electric signal converter and terminating the mask period after the variable threshold for identifying the optical signal for the subsequent burst data set is determined, and

said phase determination unit has first means for detecting the optimum phase data train in each cycle of said reference clock, and second means for cumulatively summing the number of times the optimum phase data train is detected by said first means for each of the different phases and generating, regarding the phase for which the cumulative sum reaches a reference value as the optimum phase, a control signal indicating said optimum phase data train,

said second means clearing the number of detections for each of the different phases on every determination of the optimum phase, repeating the cumulative summation of the number of detections for each of the different phases, and maintaining, during the mask period indicated by said mask signal, a state in which the number of detections is cleared while halting the operation of cumulative summation of the number of detections.