Wireless device having dual bus archeticure for interfacing with cellular signals and short-range radio signals
First Claim
1. ) A device, comprising:
- a first bus;
a first transceiver, coupled to the first bus, capable to transmit and receive a cellular signal responsive to a first control signal;
a first processor, coupled to the first bus, capable to generate the first control signal;
a second bus;
a second transceiver, coupled to the second bus, capable to transmit and receive short-range radio signal responsive to a second control signal;
a second processor, coupled to the second bus, capable to generate a second control signal; and
, a third bus coupled between the first processor and second processor.
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Accused Products
Abstract
A wireless device having dual bus architecture for interfacing with cellular signals and short-range radio signals is provided in an embodiment of the present invention. A first bus couples a first processor to a first transceiver capable to transmit and receive cellular signals. A second bus couples a second processor to a second transceiver capable to transmit and receive short-range radio signals. A third bus is coupled to the first processor and the second processor for transferring multiplexed commands and data. A fourth bus is coupled to the first processor and the second processor for transferring an audio signal, such as a human voice. In an embodiment of the present invention, each processor has a universal a synchronous receiver-transmitter (“UART”) coupled to the third bus, such as a RS-232 bus, and the fourth bus is a pulse code modulation (“PCM”) bus. A first memory device is coupled to the second bus and stores a microrouter software component for transferring an Internet protocol (“IP”) packet.
121 Citations
36 Claims
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1. ) A device, comprising:
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a first bus;
a first transceiver, coupled to the first bus, capable to transmit and receive a cellular signal responsive to a first control signal;
a first processor, coupled to the first bus, capable to generate the first control signal;
a second bus;
a second transceiver, coupled to the second bus, capable to transmit and receive short-range radio signal responsive to a second control signal;
a second processor, coupled to the second bus, capable to generate a second control signal; and
,a third bus coupled between the first processor and second processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. ) A handheld device, comprising:
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a first bus;
a first transceiver, coupled to the first bus, capable to transmit and receive a cellular signal responsive to a first control signal;
a first processor, coupled to the first bus, capable to generate the first control signal;
a first memory, coupled to the first bus, capable to store a cellular software component to generate the cellular signal using a predetermined cellular protocol;
a second bus;
a second transceiver, coupled to the second bus, capable to transmit and receive short-range radio signal responsive to a second control signal;
a second processor, coupled to the second bus, capable to generate a second control signal;
a second memory, coupled to the second bus, capable to store a router software component to transfer a packet;
a UART bus, coupled between the first processor and the second processor, to transfer an AT command and data packet; and
, a PCM bus, coupled between the first processor and the second processor, to transfer voice. - View Dependent Claims (24, 25, 26, 27)
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28. ) A device, comprising:
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a first bus;
a first transceiver, coupled to the first bus, capable to transmit and receive a cellular signal responsive to a first control signal;
a first processor, coupled to the first bus, capable to generate the first control signal;
a second bus;
a second transceiver, coupled to the second bus, capable to transmit and receive short-range radio signal responsive to a second control signal;
a second processor, coupled to the second bus, capable to generate a second control signal, wherein the second processor includes a first memory storing a router software component; and
,a third bus coupled between the first processor and second processor, wherein the first processor generates consecutively a first AT command, data, and a second AT command on the third bus to the second processor. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35)
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36. ) A device, comprising:
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a first bus;
a first processor having a memory device storing an application-software component, coupled to the first bus;
a second bus;
a first transceiver, coupled to the second bus, capable to transmit and receive short-range radio signal responsive to a first control signal;
a second processor, coupled to the second bus, capable to generate the first control signal; and
,a third bus coupled between the first processor and second processor, wherein the first processor generates consecutively a first AT command, data, and a second AT command on the third bus to the second processor.
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Specification