Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation
First Claim
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1. A microprocessor, comprising:
- a processing element configured to process an application using a bandwidth;
an access shaper coupled to said processing element and configured to shape storage requests for said processing of said application; and
bandwidth management circuitry coupled to said access shaper and configured to track said bandwidth usage based on said requests.
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Abstract
The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.
90 Citations
20 Claims
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1. A microprocessor, comprising:
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a processing element configured to process an application using a bandwidth;
an access shaper coupled to said processing element and configured to shape storage requests for said processing of said application; and
bandwidth management circuitry coupled to said access shaper and configured to track said bandwidth usage based on said requests. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of managing bandwidth allocation within a microprocessor, comprising:
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processing an application using a bandwidth with a processing element;
shaping storage requests for said processing using an access shaper coupled to said processing element; and
tracking said bandwidth usage with bandwidth management circuitry coupled to said access shaper, based on said requests. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A processor assembly, comprising:
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a bridge chip configured to control access to a memory element;
a plurality of microprocessors coupled to said bridge chip using a bus interface and configured to store and retrieve data in said memory element, each of said microprocessors comprising;
a plurality of processing elements coupled to an internal interconnect and configured to process corresponding applications each using a corresponding bandwidth;
a plurality of access shapers coupled to each of said processing elements and each configured to shape corresponding storage requests for said processing of said applications within said corresponding bandwidth; and
bandwidth management circuitry coupled to said plurality of access shapers and configured to track usage of said corresponding bandwidths based on each of said requests. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification