Reconfigurable memory module and method

• US 20040260864A1
• Filed: 06/19/2003
• Published: 12/23/2004
• Est. Priority Date: 06/19/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., Lee, Terry R.
• Granted Patent: US 7,120,727 B2
• Time in Patent Office: Days
• US Class Current: 711/101
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol

Abstract

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Claims

1. A memory module, comprising:

a plurality of memory devices arranged in a plurality of ranks; and

a memory hub coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of data formats each corresponding to a respective number of ranks of memory devices that are simultaneously accessed.

2. The memory module of claim 1 wherein the memory hub is coupled to the memory devices in each of the ranks through respective busses.

3. The memory module of claim 1 wherein the memory hub is operable to either address all of the ranks of memory devices in a first mode to simultaneously couple data to or from all of the memory devices in the memory module, or address less than all of the ranks of memory devices in a second mode to couple data to or from less than all of the memory devices in the memory module.

4. The memory module of claim 1 wherein the memory module comprises four ranks of memory devices, and wherein the memory hub is operable to simultaneously address all of four ranks of memory devices in a first mode to simultaneously couple data to or from all of the memory devices in the memory module, to simultaneously address two ranks of memory devices in a second mode to simultaneously couple data to or from the memory devices in the two addressed ranks, or to address one rank of memory devices in a third mode to couple data to or from the memory devices in the addressed rank.

5. The memory module of claim 1, further comprising a programmable storage device coupled to the memory hub, the programmable storage device being programmed to control the operating mode of the memory hub.

6. The memory module of claim 1 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory hub further comprises an input/output port that is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory module.

7. The memory module of claim 1 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory hub further comprises an input/output port that is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

8. The memory module of claim 7 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises an N-bit input/output port that is operable to transmit or receive N-bit data words at a rate of M*X data words per second.

9. The memory module of claim 7 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises a 2*N-bit input/output port that is operable to transmit or receive 2*N-bit data words at a rate of M*X/2 data words per second.

10. The memory module of claim 7 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises a M*N-bit input/output port that is operable to transmit or receive M*N-bit data words at a rate of X data words per second.

11. The memory module of claim 1 wherein the memory devices comprise dynamic random access memory devices.

12. The memory module of claim 11 wherein the dynamic random access memory devices comprise synchronous dynamic random access memory devices.

13. A memory system, comprising:

a controller operable to receive a memory request and to transmit a corresponding memory request to an input/output port;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of ranks; and

a memory hub operable to receive a memory request at an input/output port, the memory hub being coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of data formats each corresponding to a respective number of ranks of memory devices that are simultaneously accessed; and

a communications link coupling the input/output port of the controller to the input/output ports of the memory hubs in the respective memory modules.

14. The memory system of claim 13 wherein the memory hub in each of the memory modules is coupled to the memory devices in each of the ranks through respective busses.

15. The memory system of claim 13 wherein the memory hub is operable to either address all of the ranks of memory devices in a first mode to simultaneously couple data to or from all of the memory devices in the memory module, or address less than all of the ranks of memory devices in a second mode to couple data to or from less than all of the memory devices in the memory module.

16. The memory system of claim 13 wherein the memory module comprises four ranks of memory devices, and wherein the memory hub is operable to simultaneously address all of four ranks of memory devices in a first mode to simultaneously couple data to or from all of the memory devices in the memory module, to simultaneously address two ranks of memory devices in a second mode to simultaneously couple data to or from the memory devices in the two addressed ranks, or to address one rank of memory devices in a third mode to couple data to or from the memory devices in the addressed rank.

17. The memory system of claim 13, further comprising a programmable storage device coupled to the memory hub, the programmable storage device being programmed to control the operating mode of the memory hub.

18. The memory system of claim 13 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory hub further comprises an input/output port that is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory module.

19. The memory system of claim 13 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory hub further comprises an input/output port that is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

20. The memory system of claim 19 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises an N-bit input/output port that is operable to transmit or receive N-bit data words at a rate of M*X data words per second.

21. The memory system of claim 19 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises a 2*N-bit input/output port that is operable to transmit or receive 2*N-bit data words at a rate of M*X/2 data words per second.

22. The memory system of claim 19 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises a M*N-bit input/output port that is operable to transmit or receive M*N-bit data words at a rate of X data words per second.

23. The memory system of claim 13 wherein the memory devices comprise dynamic random access memory devices.

24. The memory system of claim 23 wherein the dynamic random access memory devices comprise synchronous dynamic random access memory devices.

25. The memory system of claim 13 wherein the memory hubs in at least two of the memory modules are programmed to configure the memory module in different data formats.

26. The memory system of claim 25 wherein the memory hub in a first of the memory modules is programmed to configure the first memory module so that all of the ranks of memory devices in the first memory module are simultaneously addressed, the memory hub in a second of the memory modules is programmed to configure the second memory module so that half of the ranks of memory devices in the second memory module are simultaneously addressed, and the memory hub in a third of the memory modules is programmed to configure the third memory module so that each of the ranks of memory devices in the third memory module are individually addressed.

27. The memory system of claim 13 wherein the input/output port of the controller and the input/output port of each of the memory hubs comprises an optical input/output port, and wherein the communications link comprises an optical communications link.

28. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller being operable to receive a memory request from the central processing unit and to transmit a corresponding memory request to an input/output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of ranks; and

a memory hub operable to receive a memory request at an input/output port, the memory hub being coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of data formats each corresponding to a respective number of ranks of memory devices that are simultaneously accessed; and

a communications link coupling the input/output port of the system controller to the input/output ports of the memory hubs in the respective memory modules.

29. The computer system of claim 28 wherein the memory hub in each of the memory modules is coupled to the memory devices in each of the ranks through respective busses.

30. The computer system of claim 28 wherein the memory hub is operable to either address all of the ranks of memory devices in a first mode to simultaneously couple data to or from all of the memory devices in the memory module, or address less than all of the ranks of memory devices in a second mode to couple data to or from less than all of the memory devices in the memory module.

31. The computer system of claim 28 wherein the memory module comprises four ranks of memory devices, and wherein the memory hub is operable to simultaneously address all of four ranks of memory devices in a first mode to simultaneously couple data to or from all of the memory devices in the memory module, to simultaneously address two ranks of memory devices in a second mode to simultaneously couple data to or from the memory devices in the two addressed ranks, or to address one rank of memory devices in a third mode to couple data to or from the memory devices in the addressed rank.

32. The computer system of claim 28, further comprising a programmable storage device coupled to the memory hub, the programmable storage device being programmed to control the operating mode of the memory hub.

33. The computer system of claim 28 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory hub further comprises an input/output port that is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory module.

34. The computer system of claim 28 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory hub further comprises an input/output port that is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

35. The computer system of claim 34 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises an N-bit input/output port that is operable to transmit or receive N-bit data words at a rate of M*X data words per second.

36. The computer system of claim 34 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises a 2*N-bit input/output port that is operable to transmit or receive 2*N-bit data words at a rate of M*X/2 data words per second.

37. The computer system of claim 34 wherein the memory devices are operable to read or write data at a rate of X bits per second, and wherein the input/output port comprises a M*N-bit input/output port that is operable to transmit or receive M*N-bit data words at a rate of X data words per second.

38. The computer system of claim 28 wherein the memory devices comprise dynamic random access memory devices.

39. The computer system of claim 38 wherein the dynamic random access memory devices comprise synchronous dynamic random access memory devices.

40. The computer system of claim 28 wherein the memory hubs in at least two of the memory modules are programmed to configure the memory module in different data formats.

41. The computer system of claim 40 wherein the memory hub in a first of the memory modules is programmed to configure the first memory module so that all of the ranks of memory devices in the first memory module are simultaneously addressed, the memory hub in a second of the memory modules is programmed to configure the second memory module so that half of the ranks of memory devices in the second memory module are simultaneously addressed, and the memory hub in a third of the memory modules is programmed to configure the third memory module so that each of the ranks of memory devices in the third memory module are individually addressed.

42. The computer system of claim 28 wherein the input/output port of the system controller and the input/output port of each of the memory hubs comprises an optical input/output port, and wherein the communications link comprises an optical communications link.

43. A method of accessing data in a memory module containing a plurality of memory devices, the method comprising:

dividing the memory devices into a plurality of ranks;

configuring the memory module to access the data stored in the memory module in a first data format in which a first number of ranks of memory devices are simultaneously accessed; and

configuring the memory module to access the data stored in the memory module in a second data format in which a second number of ranks of memory devices are simultaneously accessed, the second number being different from the first.

44. The method of claim 43 wherein the act of configuring the memory module to access the data stored in the memory module in the first data format comprises configuring the memory module to simultaneously access all of the ranks of memory devices in the memory module so that data are simultaneously coupled to or from all of the memory devices in the memory module, and wherein the act of configuring the memory module to access the data stored in the memory module in the second data format comprises configuring the memory module to individually access each of the ranks of memory devices in the memory module so that data are simultaneously coupled to or from only the memory devices in a single rank of memory devices.

45. The method of claim 43, further comprising configuring the memory module to simultaneously access a plurality but less than all of the ranks of memory devices in the memory module so that data are simultaneously coupled to or from all of the memory devices in a plurality of ranks of memory devices but less than all of the memory devices in the memory module.

46. The method of claim 43 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the method further comprises receiving or transmitting M*N-bit data words from the memory module, where M is the number of ranks of memory devices in the memory module.

47. The method of claim 43 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the method further comprises receiving at the memory module or transmitting from the memory module M N-bit data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

48. The method of claim 47 wherein the memory devices in the memory module are operable to read or write data at a rate of X bits per second, and wherein the method further comprises receiving at the memory module or transmitting from the memory module N-bit data words data at a rate of M*X data words per second.

49. The method of claim 47 wherein the memory devices in the memory module are operable to read or write data at a rate of X bits per second, and wherein the method further comprises receiving at the memory module or transmitting from the memory module 2*N-bit data words data at a rate of M*X/2 data words per second.

50. The method of claim 47 wherein the memory devices in the memory module are operable to read or write data at a rate of X bits per second, and wherein the method further comprises receiving at the memory module or transmitting from the memory module M*N-bit data words data at a rate of X data words per second.

51. In a computer system, a method of accessing data in a plurality of memory modules each of which contains a plurality of memory devices, the method comprising:

dividing the memory devices in each of the memory modules into a plurality of ranks;

configuring each of the memory modules to access the data stored in the memory module in one of a plurality of data formats each corresponding to a respective number of ranks of memory devices that are simultaneously accessed; and

accessing data in each of the memory modules in the configured data format.

52. The method of claim 51 wherein the act of configuring the memory modules to access the data stored in the memory modules in one of a plurality of data formats comprises configuring at least one of the memory modules to simultaneously access all of the ranks of memory devices in the memory module so that data are simultaneously coupled to or from all of the memory devices in the memory module.

53. The method of claim 51 wherein the act of configuring the memory modules to access the data stored in the memory modules in one of a plurality of data formats comprises configuring at least one of the memory modules to individually access each of the ranks of memory devices in the memory module so that data are simultaneously coupled to or from only the memory devices in a single rank of memory devices.

54. The method of claim 51 wherein the act of configuring the memory modules to access the data stored in the memory modules in one of a plurality of data formats comprises configuring at least one of the memory modules to simultaneously access a plurality but less than all of the ranks of memory devices in the memory module so that data are simultaneously coupled to or from all of the memory devices in a plurality of ranks of memory devices but less than all of the memory devices in the memory module.

55. The method of claim 51 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the method further comprises receiving or transmitting M*N-bit data words from each of the memory modules, where M is the number of ranks of memory devices in the memory module.

56. The method of claim 51 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the method further comprises receiving at each of the memory modules or transmitting from each of the memory modules M N-bit data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

57. The method of claim 56 wherein the memory devices in each of the memory modules are operable to read or write data at a rate of X bits per second, and wherein the method further comprises receiving at each of the memory modules or transmitting from each of the memory modules N-bit data words data at a rate of M*X data words per second.

58. The method of claim 56 wherein the memory devices in each of the memory modules are operable to read or write data at a rate of X bits per second, and wherein the method further comprises receiving at each of the memory modules or transmitting from each of the memory modules 2*N-bit data words data at a rate of M*X/2 data words per second.

59. The method of claim 56 wherein the memory devices in each of the memory modules are operable to read or write data at a rate of X bits per second, and wherein the method further comprises receiving at each of the memory modules or transmitting from each of the memory modules M*N-bit data words data at a rate of X data words per second.

60. The method of claim 51 wherein the act of configuring each of the memory modules comprises configuring at least two of the memory modules for different data formats.

61. The method of claim 60 wherein the act of configuring at least two of the memory modules for different data formats comprises configuring a first memory module so that all of the ranks of memory devices in the first memory module are simultaneously addressed, configuring a second memory module so that half of the ranks of memory devices in the second memory module are simultaneously addressed, and configuring a third memory module so that each of the ranks of memory devices in the third memory module are individually addressed.