Posted write buffers and methods of posting write requests in memory modules

• US 20040260891A1
• Filed: 06/20/2003
• Published: 12/23/2004
• Est. Priority Date: 06/20/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., Lee, Terry R.
• Granted Patent: US 7,107,415 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared to subsequent read request addresses. In the event of a positive comparison indicating that a read request is directed to an address to which an earlier write request was directed, the read data are provided from the buffer. When the memory devices are not busy servicing read request, the write requests can be transferred from the posted write buffer to the memory devices. The write requests may also be accumulated in the posted write buffer until either a predetermined number of write requests have been accumulated or the write requests have been posted for a predetermined duration.

Claims

1. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface receiving memory requests for access to at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;

a posted write buffer coupled to the link interface and the memory device interface, the posted write buffer being operable to store write memory requests and to subsequently couple the write memory requests to the memory device interface; and

a read request path operable to couple read memory requests from the link interface to the memory device interface and to couple read data from the memory device interface to the link interface.

2. The memory module of claim 1 wherein the read request path comprises a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface.

3. The memory module of claim 2 wherein the posted write buffer comprises coherency circuitry that is operable to receive read memory requests from the link interface and is operable to determine if read data called for by the read request is stored in the posted write buffer and to generate a hit signal responsive thereto, and wherein the memory sequencer is coupled to receive the hit signal from the posted write buffer and is operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface only in the absence of the hit signal.

4. The memory module of claim 1 wherein the posted write buffer is operable to couple the write memory requests to the memory device interface only when neither the memory hub nor the memory devices are busy servicing read memory requests.

5. The memory module of claim 1 wherein the posted write buffer further comprises coherency circuitry coupled to receive read memory requests from the link interface, the coherency circuitry being operable to determine from each read memory request whether the read memory request is directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface, the coherency circuitry being operable to couple the read data responsive to the read memory request from the posted write buffer to the link interface in the event the read memory request is directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface.

6. The memory module of claim 1 wherein the memory hub further comprises a multiplexer having a first input port coupled to receive read data from the posted write buffer, a second input port coupled to receive read data from the memory device interface and an output port coupled to the link interface to apply read data to the link interface, the multiplexer further having a control terminal coupled to the posted write buffer, the posted write buffer generating a control signal to cause the multiplexer to couple the output port to the first input port in the event the read memory request is directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface, and to generate a control signal to cause the multiplexer to couple the output port to the second input port in the event the read memory request is not directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface.

7. The memory module of claim 1 wherein the posted write buffer is operable to store posted write memory requests until the number of posted write memory requests accumulated exceeds a predetermined number, and to thereafter couple the posted write memory requests to the memory device interface.

8. The memory module of claim 7 wherein the posted write buffer is operable to vary the predetermined number as a function of an operating parameter of the memory module.

9. The memory module of claim 1 wherein the posted write buffer is operable to store posted write memory requests until the posted write memory requests have been stored for more than a predetermined duration, and to thereafter couple the posted write memory requests to the memory device interface.

10. The memory module of claim 9 wherein the posted write buffer is operable to vary the predetermined duration as a function of an operating parameter of the memory module.

11. The memory module of claim 1 wherein the posted write buffer is operable to store posted write memory requests as long as the number of posted write memory requests accumulated does not exceed a predetermined number and the posted write memory requests have not been stored for more than a predetermined duration, and to couple the posted write memory requests to the memory device interface if either the number of posted write memory requests accumulated exceeds the predetermined number or the posted write memory requests have been stored for more than the predetermined duration.

12. The memory module of claim 1 wherein the link interface comprises an optical input/output port.

13. The memory module of claim 1 wherein the memory devices comprise dynamic random access memory devices.

14. A memory hub, comprising:

a link interface receiving memory requests;

a memory device interface operable to output memory requests and to receive read data responsive to the memory requests output by the memory device interface;

a posted write buffer coupled to the link interface and the memory device interface, the posted write buffer being operable to store write memory requests and to subsequently couple the write memory requests to the memory device interface; and

a read request path operable to couple read memory requests from the link interface to the memory device interface and to couple read data from the memory device interface to the link interface.

15. The memory hub of claim 14 wherein the read request path comprises a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface.

16. The memory hub of claim 15 wherein the posted write buffer comprises coherency circuitry that is operable to receive read memory requests from the link interface and is operable to determine if read data called for by the read request is stored in the posted write buffer and to generate a hit signal responsive thereto, and wherein the memory sequencer is coupled to receive the hit signal from the posted write buffer and is operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface only in the absence of the hit signal.

17. The memory hub of claim 14 wherein the posted write buffer is operable to couple the write memory requests to the memory device interface only when neither the memory hub nor the memory devices are busy servicing read memory requests.

18. The memory hub of claim 14 wherein the posted write buffer further comprises coherency circuitry coupled to receive read memory requests from the link interface, the coherency circuitry being operable to determine from each read memory request whether the read memory request is directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface, the coherency circuitry being operable to couple the read data responsive to the read memory request from the posted write buffer to the link interface in the event the read memory request is directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface.

19. The memory hub of claim 14 wherein the memory hub further comprises a multiplexer having a first input port coupled to receive read data from the posted write buffer, a second input port coupled to receive read data from the memory device interface and an output port coupled to the link interface to apply read data to the link interface, the multiplexer further having a control terminal coupled to the posted write buffer, the posted write buffer generating a control signal to cause the multiplexer to couple the output port to the first input port in the event the read memory request is directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface, and to generate a control signal to cause the multiplexer to couple the output port to the second input port in the event the read memory request is not directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface.

20. The memory hub of claim 14 wherein the posted write buffer is operable to store posted write memory requests until the number of posted write memory requests accumulated exceeds a predetermined number, and to thereafter couple the posted write memory requests to the memory device interface.

21. The memory module of claim 20 wherein the posted write buffer is operable to vary the predetermined number as a function of an operating parameter of the memory hub.

22. The memory hub of claim 14 wherein the posted write buffer is operable to store posted write memory requests until the posted write memory requests have been stored for more than a predetermined duration, and to thereafter couple the posted write memory requests to the memory device interface.

23. The memory hub of claim 22 wherein the posted write buffer is operable to vary the predetermined duration as a function of an operating parameter of the memory module.

24. The memory hub of claim 14 wherein the posted write buffer is operable to store posted write memory requests as long as the number of posted write memory requests accumulated does not exceeds a predetermined number and the posted write memory requests have not been stored for more than a predetermined duration, and to couple the posted write memory requests to the memory device interface if either the number of posted write memory requests accumulated exceeds the predetermined number or the posted write memory requests have been stored for more than the predetermined duration.

25. The memory hub of claim 14 wherein the link interface comprises an optical input/output port.

26. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices; and

a memory hub, comprising;

a link interface receiving memory requests for access to at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;

a posted write buffer coupled to the link interface and the memory device interface, the posted write buffer being operable to store write memory requests and to subsequently couple the write memory requests to the memory device interface; and

a read request path operable to couple read memory requests from the link interface to the memory device interface and to couple read data from the memory device interface to the link interface; and

a communications link coupled between the system controller and each of the memory modules for coupling memory requests and read data between the system controller and the memory modules in the respective memory modules.

27. The computer system of claim 26 wherein the read request path comprises a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface.

28. The computer system of claim 27 wherein the posted write buffer comprises coherency circuitry that is operable to receive read memory requests from the link interface and is operable to determine if read data called for by the read request is stored in the posted write buffer and to generate a hit signal responsive thereto, and wherein the memory sequencer is coupled to receive the hit signal from the posted write buffer and is operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface only in the absence of the hit signal.

29. The computer system of claim 26 wherein the posted write buffer is operable to couple the write memory requests to the memory device interface only when neither the memory hub nor the memory devices are busy servicing read memory requests.

30. The computer system of claim 26 wherein the posted write buffer further comprises coherency circuitry coupled to receive read memory requests from the link interface, the coherency circuitry being operable to determine from each read memory request whether the read memory request is directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface, the coherency circuitry being operable to couple the read data responsive to the read memory request from the posted write buffer to the link interface in the event the read memory request is directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface.

31. The computer system of claim 26 wherein the memory hub further comprises a multiplexer having a first input port coupled to receive read data from the posted write buffer, a second input port coupled to receive read data from the memory device interface and an output port coupled to the link interface to apply read data to the link interface, the multiplexer further having a control terminal coupled to the posted write buffer, the posted write buffer generating a control signal to cause the multiplexer to couple the output port to the first input port in the event the read memory request is directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface, and to generate a control signal to cause the multiplexer to couple the output port to the second input port in the event the read memory request is not directed to a memory address to which a write memory request has been stored in the posted write buffer and has not yet been coupled to the memory device interface.

32. The computer system of claim 26 wherein the posted write buffer is operable to store posted write memory requests until the number of posted write memory requests accumulated exceeds a predetermined number, and to thereafter couple the posted write memory requests to the memory device interface.

33. The computer system of claim 32 wherein the posted write buffer is operable to vary the predetermined number as a function of an operating parameter of the computer system.

34. The computer system of claim 26 wherein the posted write buffer is operable to store posted write memory requests until the posted write memory requests have been stored for more than a predetermined duration, and to thereafter couple the posted write memory requests to the memory device interface.

35. The computer system of claim 34 wherein the posted write buffer is operable to vary the predetermined duration as a function of an operating parameter of the computer system.

36. The computer system of claim 26 wherein the posted write buffer is operable to store posted write memory requests as long as the number of posted write memory requests accumulated does not exceeds a predetermined number and the posted write memory requests have not been stored for more than a predetermined duration, and to couple the posted write memory requests to the memory device interface if either the number of posted write memory requests accumulated exceeds the predetermined number or the posted write memory requests have been stored for more than the predetermined duration.

37. The computer system of claim 26 wherein the link interface comprises an optical input/output port.

38. The computer system of claim 26 wherein the memory devices comprise dynamic random access memory devices.

39. The computer system of claim 26 wherein the communications link comprises an optical communications link.

40. In a computer system, a method of reading data from a plurality of memory modules, comprising:

receiving memory requests at each of the plurality of memory modules, the memory requests requesting access to a memory device in the memory module, the memory requests including read requests and write requests;

coupling at least some of the read memory requests to the memory device in the memory module receiving the read request;

coupling read data from the memory module responsive to the read memory request;

accumulating the write requests in the memory module without immediately coupling the write requests to the memory devices in the memory module receiving the write request; and

subsequently coupling each of the accumulated write requests to the memory device in the memory module receiving the write request.

41. The method of claim 40, further comprising:

determining in each memory module receiving a read request if the read request is directed to a memory address for which an accumulated write request is directed but not yet coupled to the memory device;

if the read request is directed to a memory address for which an accumulated write request is directed but not yet coupled to the memory device, coupling the read data from the accumulated write requests; and

if the read request is not directed to a memory address for which an accumulated write request is directed but not yet coupled to the memory device, coupling the read data from the memory device.

42. The method of claim 40, further comprising:

determining in each memory module receiving a read request if the read request is directed to a memory address for which an accumulated write request is directed but not yet coupled to the memory device; and

if the read request is not directed to a memory address for which an accumulated write request is directed but not yet coupled to the memory device, coupling the read request to the memory device in the memory module receiving the read request.

43. The method of claim 40 wherein the act of subsequently coupling each of the accumulated write requests to the memory device in the memory module receiving the write request comprises subsequently coupling each of the accumulated write requests to the memory device in the memory module receiving the write request only when the memory device is not busy servicing a read request.

44. The method of claim 40, further comprising:

determining from each read memory request whether the read memory request is directed to a memory address to which a write memory request has been accumulated but not yet coupled to the memory device;

coupling the read data responsive to the read memory request from the accumulated write requests in the event the read memory request is directed to a memory address to which a write memory request has been accumulated but not yet coupled to the memory device.

45. The method of claim 40 wherein the act of subsequently coupling each of the accumulated write requests to the memory device in the memory module receiving the write request comprises:

accumulating write requests until the number of write requests accumulated exceeds a predetermined number; and

when the number of write requests accumulated exceeds the predetermined number, coupling the write requests to the memory device.

46. The method of claim 45, further comprising varying the predetermined number as a function of an operating parameter of the computer system.

47. The method of claim 40 wherein the act of subsequently coupling each of the accumulated write requests to the memory device in the memory module receiving the write request comprises:

accumulating write requests until the write requests have been accumulated for more than a predetermined duration;

when each of the write requests has been accumulated for more than the predetermined duration, coupling the write request to the memory device.

48. The method of claim 47, further comprising varying the predetermined duration as a function of an operating parameter of the computer system.

49. The method of claim 40 wherein the act of subsequently coupling each of the accumulated write requests to the memory device in the memory module receiving the write request comprises:

accumulating write requests until the number of write requests accumulated exceeds a predetermined number or the write requests have been accumulated for more than a predetermined duration; and

when the number of write requests accumulated exceeds the predetermined number or when a write request has been accumulated for more than the predetermined duration, coupling the write request to the memory device.

50. The method of claim 40 wherein the memory devices comprise dynamic random access memory devices.