Organic field effect transistor, method for production and use thereof in the assembly of integrated circuits

• US 20040262599A1
• Filed: 08/17/2004
• Published: 12/30/2004
• Est. Priority Date: 06/01/2001
• Status: Abandoned Application

• Current Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Original Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Inventors: Bernds, Adolf, Fix, Walter
• Application Number:
  US10/479,234
• Publication Number:
  US 20040262599A1
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/471 the gate dielectric comprising only organic materials
• CPC Class Codes: H10K 10/84 Ohmic electrodes, e.g. source or drain electrodes
• CPC Class Codes: H10K 71/13 using printing techniques, e.g. ink-jet printing or screen printing
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes
• CPC Class Codes: H10K 71/821 Patterning of a layer by embossing, e.g. stamping to form trenches in an insulating layer

Abstract

The invention relates to an OFET, in which the gate (2) and source and drain electrodes (5) are embedded in the insulation layer (3). The A structuring of the insulation layer is carried out by means of a stamping technique, with which high resolution conducting structures can be produced and the OFET has a high power capacity.

Claims

1. An organic field effect transistor comprising

a gate electrode (2)

an insulation layer (3′

)

a semiconducting layer (6),

on a substrate (1), in the preceding sequence, in which the source and drain electrode(s) are embedded in the insulation layer (3′

).

2. An organic field effect transistor in accordance with claim 1, characterized in that said insulation layer (3′

) consists of an ultraviolet or thermosetting material.

3. An organic field effect transistor in accordance with claims 1 or 2, characterized in that said insulation layer (3′

) is structured to accommodate the source and drain electrode(s) by means of a stamping technique.

4. An organic field effect transistor in accordance with one of the claims 1 through 3, characterized in that the distance 1 between source and drain electrodes is smaller than 20 μ

m, in particular smaller than 10 μ

m and preferably between 2 and 5 μ

m.

5. A method for the production of an OFET with bottom-gate structure in accordance with one of the claims 1 through 4, in which a gate electrode (2) is applied to a substrate (1), an insulation layer (3) made of a hardening material is formed above, the structure for the source and drain electrode(s) is generated in said unhardened insulation layer (3) by means of a stamp (4) and preserved through hardening of the insulation material, the preserved structure is filled with a conductive material and the semiconducting layer (6) is formed on top.

6. A method in accordance with claim 5 characterized in that the hardened material for said insulating layer (3′

) is selected from expoxies and/or acrylates.

7. A method in accordance with claim 5 or 6 characterized in that the conducting material for the formation of electrodes is selected from conducting organic materials and particle-filled polymers.

8. A method in accordance with one of the claims 5 through 7 characterized in that the conducting material is squeegeed into the predetermined structure for said insulator (3′

).

9. A method in accordance with one of the claims 5 through 8, which is carried out as a continuous method with a continuous belt.

10. Use of an OFET in accordance with one of the claims 1 through 4 or 5 through 9 in the assembly of integrated circuits.