Three-dimensional integrated circuit structure and method of making same

• US 20040262635A1
• Filed: 06/21/2004
• Published: 12/30/2004
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: Sang-Yun Lee
• Inventors: Lee, Sang-Yun
• Granted Patent: US 7,052,941 B2
• Time in Patent Office: Days
• US Class Current: 257/199
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/34 : of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate. The plurality of vertically oriented semiconductor devices may be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures. Alternatively, the plurality of vertically oriented semiconductor devices may be fabricated prior to attachment to the separately fabricated substrate. The doped stack structures may form the basis for diodes, capacitors, n-MOSFETs, p-MOSFETs, bipolar transistors, and floating gate transistors. Ferroelectric memory devices, Ferromagnetic memory devices, chalcogenide phase change devices, may be formed in a stackable add-on layer for use in conjunction with a separately fabricated substrate. Stackable add-on layers may include interconnect lines.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate having electrical devices formed therein, and further having at least one dielectric layer and at least one interconnect layer disposed above the substrate;

providing a first stackable add-on layer, the first stackable add-on layer including a plurality of vertically oriented semiconductor devices disposed within the first stackable add-on layer, the plurality of vertically oriented semiconductor devices separated from each other by dielectric material; and

attaching the stackable add-on layer to a layer of the substrate that is the greatest distance from the substrate.

2. The method of claim 1, wherein the plurality of vertically oriented semiconductor devices includes at least one n-p-n stack.

3. The method of claim 2, further comprising forming a gate dielectric on the n-p-n stack, and forming a gate electrode on the gate dielectric.

4. The method of claim 3, wherein the gate electrode is disposed on the gate dielectric such that it is adjacent at least a p region of the n-p-n stack so as to form an n-type MOSFET.

5. The method of claim 1, wherein the plurality of vertically oriented semiconductor devices includes at least one p-n-p stack.

6. The method of claim 5, further comprising forming a gate dielectric on the p-n-p stack, and forming a gate electrode on the gate dielectric.

7. The method of claim 6, wherein the gate electrode is disposed on the gate dielectric such that it is adjacent at least an n region of the p-n-p stack so as to form a p-type MOSFET.

8. The method of claim 1, wherein the plurality of vertically oriented semiconductor devices includes at least one floating gate non-volatile memory device.

9. The method of claim 8, wherein a vertically oriented erase gate is disposed adjacent the at least one floating gate non-volatile memory device.

10. The method of claim 1, further comprising attaching a second stackable add-on layer above the first stackable add-on layer.

11. A method of forming a stackable add-on layer, comprising:

forming a detach layer in a first semiconductor substrate;

forming a plurality of doped regions in the first semiconductor substrate above the detach layer;

wherein forming the plurality of doped layers comprises;

forming a first doped layer in the first semiconductor substrate above the detach layer, the first doped layer being doped so as to have a first conductivity type;

forming at least an intermediate doped layer in the first semiconductor substrate above the first doped layer, the intermediate doped layer being doped so as to have a second conductivity type which is opposite the first conductivity type; and

forming at least a third doped layer in the first semiconductor substrate above the intermediate doped layer;

forming a first electrically conductive blanket layer over the third doped layer;

forming a second electrically conductive blanket layer over the first electrically conductive blanket layer; and

attaching the first semiconductor substrate to a second semiconductor substrate such that the second electrically conductive blanket layer is in contact with a corresponding electrically conductive top layer of the second semiconductor substrate.

12. The method of claim 11, further comprising:

removing a portion of the first substrate that is on a side of the detach layer opposite the side on which the first doped layer is disposed, such that the first doped layer is exposed.

13. The method of claim 12, further comprising:

forming a third electrically conductive blanket layer over the exposed portion of the first doped layer.

14. The method of claim 13, further comprising:

etching portions of the third electrically conductive blanket layer, thereby exposing a surface of the underlying plurality of doped regions;

etching the exposed portions of the plurality of doped layers that are not masked by unetched portions of the third electrically conductive blanket layer, thereby forming a plurality of individual doped stack structures, and exposing portions of the first electrically conductive blanket layer that are not masked by the individual doped stack structures; and

etching the exposed portions of the first electrically conductive blanket layer.

15. The method of claim 14, further comprising:

disposing a first layer of dielectric material between the individual doped stack structures, such that the first layer of dielectric material surrounds the third doped layer and a portion of the intermediate doped layer of each of the individual doped stacks, and such that at least a portion of the intermediate doped layer is exposed; and

forming at least one electrically conductive line that is electrically connected to the exposed intermediate doped layer of at least one of the plurality of individual doped stack structures.

16. The method of claim 15, further comprising:

disposing a second layer of dielectric material over the first layer of dielectric material.

17. The method of claim 14, further comprising:

forming a gate dielectric layer around at least a portion of at least one doped stack structure; and

forming a gate electrode adjacent at least a portion of the gate dielectric layer.

18. A semiconductor structure, comprising:

a substrate having electrical devices disposed therein, further having a plurality of dielectric and interconnection lines formed thereon, the substrate having an uppermost layer; and

a plurality of vertically oriented semiconductor devices disposed on the uppermost layer of the substrate;

wherein each of the plurality of vertically oriented semiconductor devices has a first metal electrode disposed on a bottom side thereof and a second metal electrode disposed on a top side thereof, and the plurality of vertically oriented semiconductor devices are separated from each other by a region in which a dielectric material is disposed.

19. The semiconductor structure of claim 18, wherein the vertically oriented semiconductor devices comprise a first doped region of a first conductivity type, a second doped region adjacent the first portion, the second doped region of a second conductivity type that is opposite the first conductivity type, and a third doped region spaced apart from the first doped region by at least the second doped region.

20. The semiconductor structure of claim 19, further comprising:

a gate dielectric layer disposed over at least a portion of the second doped region, and

a gate electrode disposed over the gate dielectric layer;

wherein the first and third doped regions make electrical connection through first and second metal electrodes, and the second doped region is not provided with a direct electrical contact.