Method of forming integrated circuit structures in silicone ladder polymer

• US 20040262658A1
• Filed: 07/27/2004
• Published: 12/30/2004
• Est. Priority Date: 03/21/2002
• Status: Active Grant

• Current Assignee: Robert Rasmussen
• Original Assignee: Robert Rasmussen
• Inventors: Rasmussen, Robert
• Granted Patent: US 7,544,986 B2
• Time in Patent Office: Days
• US Class Current: 257/300
• CPC Class Codes: G03F 7/0757 Macromolecular compounds containing Si-O, Si-C or Si-N bonds G03F7/0752 takes precedence
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/3121 Layers comprising organo-silicon compounds
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/7687 Thin films associated with contacts of capacitors
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method of forming integrated circuit structures, such as capacitors and conductive plugs, within contact openings formed in a photosensitive silicone ladder polymer (PVSQ) is disclosed. Contact openings with reduced striations and CD loss are formed in a photosensitive silicone ladder polymer (PVSQ) layer by patterning the PVSQ film employing a photomask with a predefined pattern, exposing the PVSQ film to i-line, developing the exposed PVSQ film in a mixture of anisole/xylene in a ratio of about 1:2 for about 30 seconds, and subsequently optionally annealing the undeveloped PVSQ film at a temperature of about 300° C. to about 600° C.

Claims

1-64. -64. (Canceled)

65. A memory device comprising:

a substrate;

a memory cell formed over said substrate, said memory cell comprising a transistor including a gate provided on said substrate, and source/drain regions provided in said substrate disposed adjacent to said gate;

a conductive plug formed in an opening of a photosensitive silicone ladder polymer layer and electrically coupled to on of said source/drain regions; and

a capacitor electrically coupled to said conductive plug.

66. The memory device of claim 65, wherein said capacitor is an MIM capacitor.

67. The memory device of claim 65, wherein said capacitor is an MIS capacitor.

68. The memory device of claim 65, wherein said capacitor is an SIS capacitor.

69. The memory device of claim 65, wherein said photosensitive silicone ladder polymer layer has a thickness of about 2,000 Angstroms to about 15,000 Angstroms.

70. The memory device of claim 69, wherein said photosensitive silicone ladder polymer layer is provided to a thickness of about 6,000 Angstroms to about 10,000 Angstroms.

71. The memory device of claim 65, wherein said memory cell is a DRAM memory.

72. The memory device of claim 65, wherein said memory cell is a SRAM memory.

73. The memory device of claim 65, wherein said memory cell is a flash memory.

74. A processor-based system comprising:

a processor; and

an integrated circuit coupled to said processor, at least one of said integrated circuit and processor comprising a photosensitive silicone ladder polymer layer, a conductive plug formed in an opening of said photosensitive silicone ladder polymer layer, and a capacitor electrically coupled to said conductive plug.

75. The processor-based system of claim 74, wherein said integrated circuit is a memory device.

76. The processor-based system of claim 75, wherein said memory device is a DRAM memory device.

77. The processor-based system of claim 75, wherein said memory device is a SRAM memory device.

78. The processor-based system of claim 75, wherein said memory device is a flash memory device.

79. The processor-based system of claim 75, wherein said capacitor is formed in an insulating photosensitive silicone ladder polymer layer.

80. A conductive structure comprising:

at least one gate structure over a substrate;

source/drain regions in said substrate and on opposite sides of said gate structure;

a first electrical element provided in a first opening of a first insulating layer and electrically coupled to one of said source/drain regions, said first insulating layer being provided over at least one of said source/drain regions; and

a second insulating layer provided over said first insulating layer, at least one of said first and second insulating layer being a photosensitive silicone ladder polymer layer.

81. The conductive structure of claim 80 further comprising a second electrical element provided in a second opening of said second insulating layer.

82. The conductive structure of claim 81, wherein said second insulating layer is a photosensitive silicone ladder polymer layer and said second electrical element is a capacitor.

83. The conductive structure of claim 80, wherein said first insulating layer is a photosensitive silicone ladder polymer layer and said first electrical element is a conductive plug.

84. The conductive structure of claim 83, wherein said second insulating layer is a photosensitive silicone ladder polymer layer and said second electrical element is a capacitor.