Electrostatic discharge protection circuit

• US 20040262689A1
• Filed: 04/23/2004
• Published: 12/30/2004
• Est. Priority Date: 06/27/2003
• Status: Abandoned Application

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Chen, Yi-Lin, Lee, An-Ming
• Application Number:
  US10/829,964
• Publication Number:
  US 20040262689A1
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

An electrostatic discharge protection circuit coupled between an I/O pad and an internal circuit of an IC. The electrostatic discharge protection circuit includes a first diode having a positive end coupled to the I/O pad, and a negative end coupled to a first supply voltage; a second diode having a positive end coupled to a second supply voltage, and a negative end coupled to the I/O pad; and a third diode having a positive end coupled to the second supply voltage, and a negative end coupled to the first-supply voltage. The breakdown voltage of the third diode is substantially smaller than the breakdown voltage of the first diode or the breakdown voltage of the second diode.

Claims

1. An electrostatic discharge protection circuit coupled between an I/O pad and an internal circuit of an IC, the electrostatic discharge protection circuit comprising:

a first diode having a positive end coupled to the I/O pad, and a negative end coupled to a first supply voltage;

a second diode having a positive end coupled to a second supply voltage, and a negative end coupled to the I/O pad; and

a third diode having a positive end coupled to the second supply voltage, and a negative end coupled to the first supply voltage;

wherein the breakdown voltage of the third diode is substantially smaller than the breakdown voltage of the first diode.

2. The electrostatic discharge protection circuit of claim 1, wherein the first diode is a diode-connected PMOS transistor.

3. The electrostatic discharge protection circuit of claim 1, wherein the second diode is a diode-connected NMOS transistor.

4. The electrostatic discharge protection circuit of claim 1, wherein the third diode is a diode-connected NMOS transistor.

5. The electrostatic discharge protection circuit of claim 4, wherein the NMOS transistor of the third diode has a P⁺ region implanted under the drain region of the NMOS transistor.

6. The electrostatic discharge protection circuit of claim 4, wherein the NMOS transistor of the third diode is a low-voltage device compared to the first diode.

7. The electrostatic discharge protection circuit of claim 1, wherein the first diode has a lower doping density than the third diode.

8. The electrostatic discharge protection circuit of claim 1, wherein the third diode is a field oxide device.

9. An electrostatic discharge protection circuit coupled between an I/O pad and an internal circuit of an IC, the electrostatic discharge protection circuit comprising:

a first diode having a positive end coupled to the I/O pad, and a negative end coupled to a first supply voltage;

a second diode having a positive end coupled to a second supply voltage, and a negative end coupled to the I/O pad; and

a third diode having a positive end coupled to the second supply voltage, and a negative end coupled to the first supply voltage;

wherein the breakdown voltage of the third diode is substantially smaller than the breakdown voltage of the second diode.

10. The electrostatic discharge protection circuit of claim 9, wherein the first diode is a diode-connected PMOS transistor.

11. The electrostatic discharge protection circuit of claim 9, wherein the second diode is a diode-connected NMOS transistor.

12. The electrostatic discharge protection circuit of claim 9, wherein the third diode is a diode-connected NMOS transistor.

13. The electrostatic discharge protection circuit of claim 12, wherein the NMOS transistor of the third diode has a P⁺ region implanted under the drain region of the NMOS transistor.

14. The electrostatic discharge protection circuit of claim 12, wherein the NMOS transistor of the third diode is a low-voltage device compared to the second diode.

15. The electrostatic discharge protection circuit of claim 9, wherein the second diode has a lower doping density than the third diode.

16. The electrostatic discharge protection circuit of claim 9, wherein the third diode is a field oxide device.