Self-testing printed circuit board comprising electrically programmable three-dimensional memory

• US 20040262731A1
• Filed: 07/21/2004
• Published: 12/30/2004
• Est. Priority Date: 10/07/2001
• Status: Active Grant

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Granted Patent: US 7,126,196 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 29/822 for read only memories
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/76 Unipolar devices , e.g. field effect transistors

Abstract

The electrically programmable three-dimensional memory (EP-3DM) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, EP-3DM has minimum impact to the layout of the CUT. Apparently, CUT with integrated EP-3DM supports IC self-test. Moreover, with a large bandwidth with the CUT, EP-3DM-based IC self-test enables at-speed test.

Claims

1. A printed-circuit-board (PCB), comprising:

a first integrated circuit (IC) chip comprising an electrically programmable three-dimensional memory (EP-3DM), said EP-3DM storing at least of a portion of test data and/or test-data seeds for at least a portion of circuitry on said PCB.

2. The PCB according to claim 1, further comprising:

a test interface for testing said EP-3DM.

3. The PCB according to claim 1, further comprising:

a second IC chip whose test data and/or test-data seeds are stored in said EP-3DM on said first IC chip.

4. A printed-circuit-board (PCB), comprising:

a first integrated circuit (IC) chip comprising an electrically programmable three-dimensional memory (EP-3DM), said EP-3DM storing at least a source of test data for at least a portion of circuitry on said PCB.

5. The PCB according to claim 4, further comprising:

a test interface for testing said EP-3DM.

6. The PCB according to claim 4, further comprising:

a second IC chip whose source of test data is stored in said EP-3DM on said first IC chip.

7. A process of testing an circuit-under-test (CUT) having an electrically programmable three-dimensional memory (EP-3DM) stacked thereon, comprising the steps of:

(A) reading input test vectors and expected test vectors from said EP-3DM;

(B) sending said input test vectors to said CUT and getting output test vectors;

(C) comparing said output test vectors with said expected test vectors.

8. The process according to claim 7, further comprising the step of built-in self-test (BIST) to said CUT.

9. The process according to claim 7, further comprising the step of external scan-test (EST) to said CUT.

10. The process according to claim 9, wherein

said EST is performed after said step (C);

and

said EST is only performed to test vectors associated with mismatched output test vectors and expected test vectors.

11. The process according to claim 7, further comprising the step of testing and correcting said EP-3DM before said step (A).