Methods for bonding wafers using a metal interlayer

• US 20040262772A1
• Filed: 06/30/2003
• Published: 12/30/2004
• Est. Priority Date: 06/30/2003
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ramanathan, Shriram, Kobrinsky, Mauro J., List, Scott, Dubin, Valery, Chebiam, Ramanan
• Application Number:
  US10/611,395
• Publication Number:
  US 20040262772A1
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/8182 Diffusion bonding
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01044 Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Embodiments of a method of bonding wafers together using a metal interlayer deposited on conductors of each wafer. Also disclosed is a wafer stack formed according to the method of wafer bonding using a metal interlayer.

Claims

1. A method comprising:

depositing a layer of a metal on a number of conductors disposed on a surface of a wafer; and

bonding the conductors of the wafer to corresponding conductors on a surface of a second wafer using the metal layer.

2. The method of claim 1, further comprising, prior to depositing the metal layer on the conductors, removing dielectric material from the surface of the wafer.

3. The method of claim 1, further comprising, prior to depositing the metal layer on the conductors, removing native oxide from the conductors.

4. The method of claim 1, wherein the conductors comprise Copper.

5. The method of claim 1, wherein the metal comprises one of Silver, Gold, Ruthenium, Osmium, Iridium, Palladium, Rhodium, and Platinum.

6. The method of claim 1, wherein the bonding of the conductors of the wafer to the corresponding conductors of the second wafer is performed at a temperature between approximately 100 and 300 degrees Celsius.

7. The method of claim 1, wherein depositing the layer of metal on the conductors comprises:

forming a blanket layer of the metal over the conductors and the surface of the wafer; and

removing the metal from the wafer surfaces.

8. The method of claim 1, wherein depositing the layer of metal on the conductors comprises selectively depositing the metal on the conductors.

9. The method of claim 8, wherein selectively depositing the metal on the conductors comprises one of an electroless plating process, an electroplating process, and a contact displacement plating process.

10. The method of claim 1, wherein the metal layer on each of the conductors comprises a number of islands.

11. The method of claim 10, wherein the islands are selectively deposited on the conductors.

12. The method of claim 10, wherein the islands are formed by a process comprising:

depositing a blanket layer of the metal over the conductors and the surface of the wafer; and

removing the blanket metal layer from the wafer surface and from portions of each conductor to form the number of islands on each conductor.

13. A method comprising:

depositing a layer of a first metal on a number of conductors disposed on a first wafer;

depositing a layer of a second metal on a number of conductors disposed on a second wafer;

aligning the first wafer with the second wafer; and

bonding the metal layer on the conductors of the first wafer with the metal layer on the conductors of the second wafer.

14. The method of claim 13, further comprising, prior to depositing the metal layer on the conductors of the first and second wafers, removing dielectric material from a surface of each of the first and second wafers.

15. The method of claim 13, further comprising, prior to depositing the metal layer on the conductors of the first and second wafers, removing native oxide from the conductors of each of the first and second wafers.

16. The method of claim 13, wherein the conductors of each of the first and second wafers comprise the same metal.

17. The method of claim 16, wherein the conductors of each of the first and second wafers comprise Copper.

18. The method of claim 13, wherein the first metal and the second metal are the same.

19. The method of claim 13, wherein the first metal and the second metal are different.

20. The method of claim 13, wherein each of the first and second metals comprises one of Silver, Gold, Ruthenium, Osmium, Iridium, Palladium, Rhodium, and Platinum.

21. The method of claim 13, wherein the bonding of the conductors of the first wafer to the corresponding conductors of the second wafer is performed at a temperature between approximately 100 and 300 degrees Celsius.

22. The method of claim 13, wherein depositing the metal layer on the conductors of each of the first and second wafers comprises:

forming a blanket metal layer over the conductors and a surface of the wafer; and

removing the blanket metal layer from the wafer surface.

23. The method of claim 13, wherein depositing the metal layer on the conductors of each of the first and second wafers comprises selectively depositing the metal layer on the conductors.

24. The method of claim 23, wherein selectively depositing the metal layer on the conductors comprises one of an electroless plating process, an electroplating process, and a contact displacement plating process.

25. The method of claim 13, wherein the metal layer on the conductors of at least one of the first and second wafers comprises a number of islands.

26. The method of claim 25, wherein the islands are selectively deposited on the conductors.

27. The method of claim 25, wherein the islands are formed by a process comprising:

depositing a blanket metal layer over each of the conductors and a surface of the wafer; and

removing the blanket metal layer from the wafer surface and from portions of each conductor to form the number of islands on each conductor.

28. A wafer stack comprising:

a first wafer including a number of conductors disposed on a surface of the first wafer, each of the conductors having a layer of metal formed thereon; and

a second wafer including a number of conductors disposed on a surface of the second wafer, each of the conductors having a layer of metal formed thereon;

wherein the metal layer of each conductor of the first wafer is bonded to the metal layer on a corresponding conductor of the second wafer.

29. The wafer stack of claim 28, wherein the conductors on each of the first and second wafers comprise the same metal.

30. The wafer stack of claim 29, wherein the conductors on each of the first and second wafers comprise Copper.

31. The wafer stack of claim 28, wherein the metal layer on each conductor of the first wafer and the metal layer on each conductor of the second wafer comprises the same metal.

32. The wafer stack of claim 28, wherein the metal layer on each conductor of the first wafer comprises a first metal and the metal layer on each conductor of the second wafer comprises a second, different metal.

33. The wafer stack of claim 28, wherein the metal layer on each conductor on each of the first and second wafers comprises one of Silver, Gold, Ruthenium, Osmium, Iridium, Palladium, Rhodium, and Platinum.

34. The wafer stack of claim 28, wherein the first and second wafers comprise the same material.

35. The wafer stack of claim 28, wherein the first wafer comprises one material and the second wafer comprises a different material.

36. The wafer stack of claim 28, wherein the first wafer includes logic circuitry and the second wafer includes memory circuitry.

37. A wafer stack comprising:

a first wafer, the first wafer having an interconnect including an uppermost dielectric layer and a number of lower dielectric layers, each lower dielectric layer including a number of conductors comprised of a first metal and the uppermost dielectric layer including a number of conductors comprised of a third metal; and

a second wafer, the second wafer having an interconnect including an uppermost dielectric layer and a number of lower dielectric layers, each lower dielectric layer including a number of conductors comprised of a second metal and the uppermost dielectric layer including a number of conductors comprised of a fourth metal;

wherein the conductors comprised of the third metal and the conductors comprised of the fourth metal are capable of bonding together at a temperature of approximately 300°

Celsius or less; and

wherein the conductors of the uppermost dielectric layer of the first wafer are bonded to the conductors of the uppermost dielectric layer of the second wafer.

38. The wafer stack of claim 37, wherein the first and second metals comprise the same metal.

39. The wafer stack of claim 38, wherein the first and second metals comprise Copper.

40. The wafer stack of claim 37, wherein the third and fourth metals comprise the same metal.

41. The wafer stack of claim 37, wherein each of the third and fourth metals comprise one of Silver, Gold, Ruthenium, Osmium, Iridium, Palladium, Rhodium, Platinum.

42. The wafer stack of claim 37, wherein the third metal comprises one of Silver, Gold, Ruthenium, Osmium, Iridium, Palladium, Rhodium, Platinum and the fourth metal comprises Copper.