Control circuit

• US 20040263127A1
• Filed: 08/13/2004
• Published: 12/30/2004
• Est. Priority Date: 12/21/2001
• Status: Active Grant

• Current Assignee: Cap-Xx Ltd.
• Original Assignee: Cap-Xx Ltd.
• Inventors: Turner, Geoffrey Alan, Smith, Trevor Anthony
• Granted Patent: US 7,042,197 B2
• Time in Patent Office: Days
• US Class Current: 320/166
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H01M 10/42 Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells H01M10/60 takes precedence
• CPC Class Codes: H01M 10/4264 with capacitors
• CPC Class Codes: H02J 7/345 using capacitors as storage or buffering devices
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A control circuit (101) is configured for use with a load in the form of hardware (102) of a laptop computer (103). Circuit (101) includes input terminals (105, 106) for electrically connecting with respective terminals (107, 108) of a battery pack (109). The battery pack (109) supplies a battery current and has a predetermined maximum operational current. Circuit (101) also includes output terminals (111, 112) for electrically connecting in parallel hardware (102) and a supercapacitor (113). A controller (115) is disposed between the input and the output terminals for allowing the battery to transfer energy to hardware (102) and supercapacitor (113) while maintaining the battery current at less than the predetermined maximum operational current.

Claims

1. A control circuit for a load, the circuit including:

input terminals for electrically connecting with respective terminals of a battery that has a predetermined maximum operational current whereby the battery supplies a battery current;

output terminals for electrically connecting in parallel the load and a supercapacitor; and

a controller being disposed between the input and the output terminals for allowing the battery to transfer energy to the load and the supercapacitor while maintaining the battery current at less than the predetermined maximum operational current.

2. A circuit according to claim 1 wherein the controller also prevents the supercapacitor from providing energy to the battery.

3. A circuit according to claim 1 that is a power-up protection circuit for a portable computing device.

4. A circuit according to claim 1 wherein the load draws a load current that varies with time, where the load current is the sum of the battery current and the current provided by the supercapacitor.

5. A circuit according to claim 4 wherein the load current is greater than or equal to zero and the controller maintains the battery current at greater or equal to zero.

6. A circuit according to claim 1 wherein the predetermined maximum operational current is an average over a given interval.

7. A circuit according to claim 1 wherein the predetermined maximum operational current is an instantaneous current.

8. A circuit according to claim 1 wherein the battery includes a plurality of battery cells.

9. A circuit according to claim 1 wherein the battery includes a protection circuit for electrically disconnecting the battery terminals from the input terminals in response to the predetermined maximum operation current being exceeded.

10. A circuit according to claim 1 wherein the controller is responsive to the battery current for varying a resistance between the input and the output terminals.

11. A circuit according to claim 10 wherein the controller includes one or more solid-state devices for varying the resistance.

12. A circuit according to claim 11 wherein at least one of the solid-state devices is a MOSFET.

13. A circuit according to claim 11 wherein the load has a start up sequence and the at least one of the solid-state devices operates in a linear mode during that sequence.

14. A circuit according to claim 11 wherein the at least one solid state device is mounted to a heat sink.

15. A control circuit for a load, the circuit including:

input terminals for electrically connecting with respective terminals of a battery that has a predetermined maximum operational current whereby the battery supplies a battery current;

output terminals for electrically connecting in parallel the load and a supercapacitor; and

a solid state device through which the battery current flows between the input and the output terminals, the transistor being responsive to the battery current for varying the resistance of the transistor and thereby allowing the battery to transfer energy to the load while maintaining the battery current at less than the predetermined maximum operational current.

16. A circuit according to claim 15 wherein the solid state device is a transistor.

17. A circuit according to claim 16 wherein the transistor is a MOSFET.

18. A circuit according to claim 17 wherein the MOSFET is mounted to a heat sink.

19. A control circuit for a computing device that derives power from a battery unit that has a battery and a protection circuit for isolating the battery from the device when predetermined maximum operational current is exceeded, the control circuit including:

input terminals for electrically connecting with respective terminals of the protection circuit to allow the battery to supply a battery current to the device;

output terminals for electrically connecting in parallel the load and a supercapacitor; and

a controller being disposed between the input and the output terminals for allowing the battery to transfer energy to the load and the supercapacitor while maintaining the battery current at less than the predetermined maximum operational current.

20. A portable computing device including:

a power source having at least two output terminals for supplying a source current of up to a predetermined maximum operational current;

computer hardware that includes a supply rail that draws a load current;

a supercapacitor in parallel with the supply rail; and

a controller being disposed between the output terminals and the supply rail for allowing the source to transfer energy to the hardware and the supercapacitor while maintaining the source current at less than the predetermined maximum operational current.

21. A control circuit for a load, the circuit including:

input terminals for electrically connecting with respective terminals of a battery that supplies a battery current, wherein the battery has a predetermined maximum operational current and a predetermined pulse current capacity;

output terminals for electrically connecting in parallel the load and a supercapacitor; and

a controller being disposed between the input and the output terminals for allowing the battery to transfer energy to the load and the supercapacitor while controlling the battery current such that the battery remains within the predetermined pulse current capacity.

22. A circuit according to claim 21 wherein the controller provides a current path for the battery current between the input and the output terminals and is responsive to both the quantum and the duration of the battery current for varying the resistance of the path.

23. A circuit according to claim 22 wherein the resistance of the path is varied once the predetermined pulse current capacitor has been reached.

24. A circuit according to claim 23 wherein the resistance of the path is varied to maintain battery current below the predetermined maximum operation current.