High-speed duty cycle test through DC measurement using a combination of relays

• US 20040263184A1
• Filed: 06/30/2003
• Published: 12/30/2004
• Est. Priority Date: 06/30/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ong, Shao Chee
• Granted Patent: US 6,943,556 B2
• Time in Patent Office: Days
• US Class Current: 324/537
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24

Abstract

According to one embodiment of the present invention, a method of high-speed duty cycle test through DC measurement using a combination of relays. The method includes: providing a plurality of relays to generate one or more duty cycle control signals; providing the duty cycle control signals to a device under test; measuring a first DC portion of a first output signal of the device under test; and dividing the first DC portion by a sum of the first DC portion and a second DC portion of a second output signal of the device under test.

Claims

1. A method comprising:

generating one or more duty cycle control signals by varying one or more voltage values and states of one or more relays receiving the values in order to simulate a poteniometer;

providing the duty cycle control signals to a device under test;

measuring a first DC portion of a first output signal of the device under test;

measuring a second DC portion of a second output signal of the device under test; and

dividing the first DC portion by a sum of the first DC portion and the second DC portion of a second output signal of the device under test.

2. The method of claim 1 wherein a ratio provided by the dividing reflects a duty cycle corresponding to the device under test.

3. The method of claim 1 wherein the second output signal is complementary to the first output signal of the device under test.

4. The method of claim 3 wherein the first output signal is a p channel output signal of the device under test.

5. The method of claim 1 further including providing a plurality of voltage sources coupled to the plurality of relays to drive the duty cycle control signals.

6. The method of claim 1 further including providing a plurality of resistors coupled between the plurality of relays and the device under test to vary a potential driving the duty cycle control signals.

7. The method of claim 1 further including providing a bias-T circuit to extract the first and second DC portions.

8. The method of claim 7 wherein the bias-T circuit includes a first inductor coupled to the first output signal to extract the first DC portion.

9. The method of claim 7 wherein the bias-T circuit includes a second inductor coupled to the second output signal to extract the second DC portion.

10. The method of claim 7 further including coupling the bias-T circuit to a PMU for DC measurement.

11. The method of claim 1 further including providing a plurality of capacitors to pass RF signals corresponding to the first and second output signals.

12. An apparatus comprising:

a plurality of relays to generate one or more duty cycle control signals by varying one or more voltage values and states of one or more relays receiving the values in order to simulate a poteniometer;

a device under test coupled to the plurality of relays to receive the duty cycle control signals;

a bias-T circuit coupled to the device under test to receive a first output signal and a second output signal of the device under test, the bias-T circuit extracting a first DC portion of the first output signal and a second DC portion of the second output signal; and

a divider to divide a value of the first DC portion by a sum of the first DC portion and the second DC portion.

13. The apparatus of claim 12 wherein a ratio provided by the divider reflects a duty cycle corresponding to the device under test.

14. The apparatus of claim 12 wherein the divider is selected from a group comprising a calculator, a computer, and a PDA.

15. The apparatus of claim 12 wherein the second output signal is complementary to the first output signal of the device under test.

16. The apparatus of claim 15 wherein the first output signal is a p channel output signal of the device under test.

17. The apparatus of claim 12 further including a plurality of voltage sources coupled to the plurality of relays to drive the duty cycle control signals.

18. The apparatus of claim 12 further including a plurality of resistors coupled between the plurality of relays and the device under test to vary a potential driving the duty cycle control signals.

19. The apparatus of claim 12 wherein the bias-T circuit includes a first inductor coupled to the first output signal to extract the first DC portion.

20. The apparatus of claim 12 wherein the bias-T circuit includes a second inductor coupled to the second output signal to extract the second DC portion.

21. The apparatus of claim 12 further including a plurality of capacitors to pass RF signals corresponding to the first and second output signals.

22. The apparatus of claim 12 wherein the first and second DC portions are measured by an ATE.

23. The apparatus of claim 12 wherein the plurality of relays reside on a TIU.

24. A computer system comprising:

a central processing unit (CPU);

a display device coupled to the CPU to display an image;

a device under test;

a plurality of relays coupled to the device under test to generate one or more duty cycle control signals, provided to the device under test, by varying one or more voltage values and states of one or more relays receiving the values in order to simulate a poteniometer; and

a bias-T circuit coupled to the device under test to receive a first output signal and a second output signal of the device under test, the bias-T circuit extracting a first DC portion of the first output signal and a second DC portion of the second output signal.

25. The computer system of claim 24 further including a divider to divide a value of the first DC portion by a sum of the first DC portion and the second DC portion.

26. The computer system of claim 25 wherein a ratio provided by the divider reflects a duty cycle corresponding to the device under test.

27. The computer system of claim 24 wherein the second output signal is complementary to the first output signal of the device under test.

28. The computer system of claim 24 wherein the first output signal is a p channel output signal of the device under test.

29. The computer system of claim 24 further including a main memory coupled to the CPU.

30. The computer system of claim 24 further including a memory coupled to the display device to store the image.