Gate driving method and apparatus for liquid crystal display panel

• US 20040263452A1
• Filed: 06/23/2004
• Published: 12/30/2004
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Kim, Sang Rae
• Granted Patent: US 7,375,718 B2
• Time in Patent Office: Days
• US Class Current: 345/87
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A gate driving method and apparatus for a liquid crystal display panel is disclosed that minimizes deterioration of picture quality caused by a variation in a gate low voltage. A liquid crystal cell matrix is defined by intersections between gate lines and data lines having corresponding thin film transistors. A gate driver applies a gate high voltage, which is at least equal to the turn-on voltages of the thin film transistors, to the gate lines in a corresponding period, and applies an independent gate low voltage to the gate lines divided into a plurality of blocks as turn-off voltages of the thin film transistors in each block.

Claims

1. A liquid crystal display panel comprising:

a liquid crystal cell matrix defined by intersections between gate lines and data lines, the gate lines divided into a plurality of blocks;

thin film transistors connected at the intersections, each thin film transistor having a turn-on voltage and a turn-off voltage; and

a gate driver for applying to the gate lines a gate high voltage in a particular time period and for applying to the gate lines independent gate low voltages for each block, the gate high voltage equaling or exceeding the turn-on voltage and the gate low voltages equaling or less than the turn-off voltage.

2. The liquid crystal display panel according to claim 1, wherein the liquid crystal cell matrix is divided into an upper block and a lower block, and the gate driver applies a first gate low voltage to the gate lines of the upper block and a second gate low voltage to the gate lines of the lower block.

3. The liquid crystal display panel according to claim 2, further comprising:

a swing voltage attenuator for inverting and amplifying the first gate low voltage fed-back through the gate driver and summing the inverted and amplified first gate low voltage with the second gate low voltage fed-back through the gate driver, thereby canceling out swing voltages of the first and second gate low voltages with respect to each other.

4. The liquid crystal display panel according to claim 2, further comprising:

a power source for generating the gate high voltage and for generating the gate low voltage to supply the gate low voltage via first and second transmission lines connected, in parallel, to an output line thereof as the first and second gate low voltages, respectively.

5. The liquid crystal display panel according to claim 4, wherein the first and second gate low voltages are set to the same level.

6. The liquid crystal display panel according to claim 2, wherein the first and second gate low voltages are applied, via different line on glass (LOG) type signal lines provided at the liquid crystal display panel, to the gate driver.

7. The liquid crystal display panel according to claim 2, wherein each of the liquid crystal cells includes:

a storage capacitor provided at an overlapping portion between a pixel electrode included therein and a pre-stage gate line.

8. A gate driving method for a liquid crystal display panel including a liquid crystal cell matrix defined by intersections between gate lines divided into a plurality of blocks and data lines, and thin film transistors at the intersections, the method comprising:

applying a gate high voltage, which is a turn-on voltage of the thin film transistors, to the gate lines in a time period; and

applying, to the gate lines, independent gate low voltages for each block, the gate low voltages being equal or lower than the turn-off voltages of the thin film transistors such that the thin film transistors are off when the gate low voltages are applied.

9. The gate driving method according to claim 8, further comprising dividing the liquid crystal cell matrix into an upper block and a lower block, and applying a first gate low voltage to the gate lines in the upper block and a second gate low voltage to the gate lines in the lower block.

10. The gate driving method according to claim 9, further comprising:

inverting and amplifying the first gate low voltage fed-back from the liquid crystal display panel; and

summing the inverted and amplified first gate low voltage with the second gate low voltage fed-back from the liquid crystal display panel, thereby canceling out swing voltages of the first and second gate low voltages with respect to each other.

11. The gate driving method according to claim 9, further comprising:

generating the gate high voltage; and

generating the gate low voltage and supplying the gate low voltage via first and second transmission lines connected in parallel as the first and second gate low voltages, respectively.

12. The gate driving method according to claim 11, further comprising setting the first and second gate low voltages to the same level.

13. The gate driving method according to claim 9, further comprising applying the first and second gate low voltages via different line on glass (LOG) type signal lines provided at the liquid crystal display panel.

14. A liquid crystal display panel comprising:

a substrate;

a liquid crystal cell matrix defined by intersections between gate lines and data lines disposed on the substrate, the gate lines divided into blocks;

thin film transistors disposed on the substrate and connected to the gate and data lines at the intersections; and

a gate driver that supplies a gate high voltage to the gate lines throughout the matrix and that supplies a gate low voltage to the gate lines of each block that are independent of the gate low voltage supplied to the gate lines of other blocks, a transition between application of the gate high voltage to the gate lines in one block and application of the gate high voltage to the gate lines in another block occurring only once each time the gate high voltages are supplied in a scan throughout the matrix, each transistor being in a non-conducting state upon application of the gate low voltage and being in a conducting state upon application of the gate high voltage.

15. The liquid crystal display panel according to claim 14, wherein the gate driver comprises a plurality of gate drive ICs that each drive a set of gate lines in one of the blocks, at least one of the gate drive ICs driving the gate lines of only one of the blocks and at least one of the gate drive ICs driving the gate lines of different blocks.

16. The liquid crystal display panel according to claim 15, wherein each gate drive IC comprises a shift register and level shifters array containing level shifters for each gate line connected with the gate drive IC.

17. The liquid crystal display panel according to claim 16, wherein half of the level shifters in the level shifter array of one of the gate drive ICs supply a first gate low voltage to the gate lines connected with the half of the level shifters and the other half of the level shifters supply a second gate low voltage that is independent of the first gate low voltage to the gate lines connected with the other half of the level shifters.

18. The liquid crystal display panel according to claim 17, wherein the level shifters in the gate drive IC that supply the first and second gate low voltages to the gate lines also supply the same gate high voltage to each of the gate lines connected with the gate drive IC that supplies the first and second gate low voltages.

19. The liquid crystal display panel according to claim 17, wherein the level shifters in the gate drive ICs other than the gate drive IC that supplies the first and second gate low voltages to the gate lines supply the same gate low voltage to each of the gate lines connected with the particular gate drive IC.

20. The liquid crystal display panel according to claim 19, wherein the gate low voltages supplied to all of the gate lines are the same.

21. The liquid crystal display panel according to claim 14, wherein the gate high voltages are sequentially supplied to the transistors throughout the matrix.

22. The liquid crystal display panel according to claim 14, further comprising a swing voltage attenuator through which one of the gate low voltages fed-back through the gate driver is inverted and amplified and then summed with another of the gate low voltages fed-back through the gate driver.

23. The liquid crystal display panel according to claim 14, wherein the different gate low voltages are supplied to the gate driver via different line on glass (LOG) type signal lines.

24. The liquid crystal display panel according to claim 23, wherein the different LOG type signal lines have substantially the same path length on the substrate.

25. The liquid crystal display panel according to claim 23, wherein a first of the blocks is supplied solely with a first gate low voltage, a second of the blocks is supplied solely with a second gate low voltage, and a first path length of a LOG-type signal line group through which the first gate low voltage is supplied to the first block is larger than a second path length of a LOG-type signal line group through which the second gate low voltage is supplied to the second block.