Microdisplay and interface on single chip

• US 20040263502A1
• Filed: 04/23/2004
• Published: 12/30/2004
• Est. Priority Date: 04/24/2003
• Status: Active Grant

• Current Assignee: Citizen Finedevice Co., Ltd. (Citizen Electronics Company Limited)
• Original Assignee: DT FLCO, Inc. (Micron Technology, Inc.)
• Inventors: Yee, Michael Wayne, Hollenbeck, David B., Dallas, James M., Malzbender, Rainer M., Larsen, Per Harold, Vickery, Earle R. III
• Granted Patent: US 7,283,105 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G02F 1/133553 Reflecting elements associated to illuminating devices G02F1/133605
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0221 with use of split matrices G09G3/3644 and G09G3/3666 take precedence
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2310/0259 with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 2320/0666 for control of colour parameters, e.g. colour temperature
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2059 : using error diffusion
• CPC Class Codes: G09G 3/2088 : with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
• CPC Class Codes: G09G 3/3413 : Details of control of colour illumination sources
• CPC Class Codes: G09G 3/3651 : using multistable liquid crystals, e.g. ferroelectric liquid crystals
• CPC Class Codes: G09G 3/3685 : Details of drivers for data electrodes
• CPC Class Codes: G09G 3/3688 : suitable for active matrices only
• CPC Class Codes: G09G 5/00 : Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators image data processing or generation, in general G06T
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G11C 11/417 : for memory cells of the field-effect type

Abstract

A microdisplay having interface circuitry on the same silicon backplane to allow it to receive digital images and video in a variety of formats and convert same to field sequential color signals for generation of full color images. It includes column data processors having a comparator for each block of N-columns of pixels. Image data is double-buffered in SRAM memory cells located beneath the pixel electrodes, but not within each pixel. The stored data is logically associated with each pixel via the column data processors. Image compression is accomplished by converting RGB data to a variant of YUV data and sampling the color components of the converted data less frequently than the luminance components. The SRAM image buffer consumes a reduced amount of power. A temperature compensation scheme allows the temperature of the microdisplay to be sensed and the drive voltage to the pixel electrodes to be varied in response thereto.

Claims

1. A microdisplay system for displaying image data, comprising:

a microdisplay having an array of pixels switchable between different display states, the microdisplay residing on a semiconductor substrate; and

a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format, the first format being a standard video signal.

2. A microdisplay system as defined in claim 1, wherein the microdisplay displays image data by sequentially displaying fields of a first color, a second color, and a third color.

3. A microdisplay system as defined in claim 1, wherein the first format includes RGB data for a pixel, followed by RGB data for a second pixel, and continuing in sequence until an entire row of RGB pixel data has been provided, followed by another row of RGB pixel data.

4. A microdisplay system as defined in claim 1, wherein the second format includes sequential fields of a first color, a second color, and a third color.

5. A microdisplay system as defined in claim 1, wherein the digital interface device converts RGB data to a data format having a luminance component and at least two chroma components.

6. A microdisplay system as defined in claim 5, wherein the microdisplay includes memory cells resident therein to store the image data in the data format having a luminance component and at least two chroma components.

7. A microdisplay system as defined in claim 6, wherein luminance data is stored for every individual pixel and chroma data is stored for groups of a plurality of pixels.

8. A microdisplay system as defined in claim 7, wherein each group of pixels includes four pixels.

9. A microdisplay system as defined in claim 8, wherein the pixels in the microdisplay are arranged in a plurality of rows and columns, and each group of four pixels includes two adjacent pixels in a particular row and two adjacent pixels in an adjacent row, so that two of the pixels are in one column and two of the pixels are in an adjacent column.

10. A microdisplay system as defined in claim 1, wherein the microdisplay includes memory cells for storing image data to be displayed, the memory cells being distributed throughout the microdisplay.

11. A microdisplay system as defined in claim 10, wherein the distributed memory cells are not necessarily located in or adjacent to any particular pixel.

12. A microdisplay system as defined in claim 10, wherein the distributed memory cells are co-located with the pixel array but are not physically associated with particular pixels in the pixel array.

13. A microdisplay system as defined in claim 12, wherein each pixel includes a reflective pixel electrode and the reflective pixel electrodes lie in a first plane, and wherein the distributed memory cells lie in a second plane that is and parallel to the first plane, and further wherein the orthogonal projection onto the second plane of at least some of the reflective pixel electrodes covers memory cells that store image information for other reflective pixel electrodes.

14. A microdisplay system as defined in claim 1, further including an illuminator and beam splitter assembly that attaches to the semiconductor substrate.

15. A microdisplay system as defined in claim 1, wherein the microdisplay includes dual memory buffers for storing two consecutive frames of image data for each pixel.

16. A microdisplay system for displaying image data, comprising:

a microdisplay having an array of pixels switchable between different display states, the microdisplay residing on a semiconductor substrate; and

a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format;

wherein the microdisplay includes memory cells for storing image data to be displayed, the memory cells being low power SRAM.

17. A microdisplay system as defined in claim 16, wherein the image data is read from the low power SRAM with voltage mode sense amplifiers.

18. A microdisplay system as defined in claim 17, wherein the voltage mode sense amplifiers include a fast precision comparator.

19. A microdisplay system for displaying image data, comprising:

a microdisplay having an array of pixels switchable between different display states, the microdisplay residing on a semiconductor substrate; and

a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format;

wherein each pixel of the microdisplay includes a pixel electrode and the pixel also includes circuitry to allow a pixel voltage supply to be used to supply a voltage to selected pixel electrodes with a magnitude that is different from a voltage supplied by a logic voltage supply used to drive the remainder of the microdisplay.

20. A microdisplay system as defined in claim 19, wherein the pixel voltage supply can be controlled to supply voltage of a magnitude less than, equal to, or greater than the logic voltage supply.

21. A microdisplay system as defined in claim 19, wherein the pixel voltage supply can be controlled to supply a variable voltage in order to compensate for one or more environmental conditions.

22. A microdisplay system as defined in claim 21, wherein one environmental condition compensated for by varying the pixel voltage supply is the temperature of the microdisplay.

23. A microdisplay system as defined in claim 22, wherein the temperature of the microdisplay is sensed electronically on the microdisplay.

24. A microdisplay system as defined in claim 23, wherein the temperature is sensed electronically by sensing the voltage drop across one or more diodes.

25. A microdisplay system for displaying image data, comprising:

a microdisplay having an array of pixels switchable between different display states, the microdisplay residing on a semiconductor substrate;

a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format; and

a non-volatile memory associated with the microdisplay that stores information specific to that particular microdisplay system so that the microdisplay can access the stored information and, based thereon, enhance the quality of images displayed by the microdisplay system.

26. A microdisplay system as defined in claim 25, wherein the non-volatile memory includes EEPROM.

27. A microdisplay system for displaying image data, comprising:

a microdisplay having an array of pixels switchable between different display states, the microdisplay residing on a semiconductor substrate; and

a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format;

wherein the array of pixels in the microdisplay is arranged in a rows and a first portion of the rows are in one group and a second portion of the rows are in a second group, and further wherein the pixels of one of the first and second group are updated with image information from a top row to a bottom row while the pixels of the other of the first and second group are updated with image information from a bottom row to a top row.

28. A microdisplay system as defined in claim 27, wherein the one of the first and second group that has its pixels updated with image information from a top row to a bottom row alternates on successive frames between the first and the second group.

29. A microdisplay system for displaying image data, comprising:

a microdisplay having an array of pixels switchable between different display states, the microdisplay residing on a semiconductor substrate; and

a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format;

wherein the microdisplay includes centralized timing circuitry, that services a plurality of pixels, where a comparison is made between a ramp counter signal and a desired pixel value for each pixel of the plurality of pixels and based thereon a separate pixel state signal for each pixel is sent to each pixel.

30. A microdisplay system as defined in claim 29, wherein there is a plurality of sets of the centralized timing circuitry, one for every N columns of pixels.

31. A microdisplay system for displaying image data, comprising:

a spatial light modulator having an array of pixels switchable between different light modulating states, the spatial light modulator residing on a semiconductor substrate; and

a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the spatial light modulator in a second format;

wherein the spatial light modulator includes memory cells for storing image data to be displayed, the memory cells being distributed throughout the spatial light modulator, wherein the distributed memory cells are co-located with the pixel array but are not physically associated with particular pixels in the pixel array, and further wherein each pixel includes a reflective pixel electrode and the reflective pixel electrodes lie in a first plane, and wherein the distributed memory cells lie in a second plane that is and parallel to the first plane, and further wherein the orthogonal projection onto the second plane of at least some of the reflective pixel electrodes covers memory cells that store image information for other reflective pixel electrodes.

32. A method of producing an image having color and gray scale, comprising:

providing an array of picture elements and an array of data storage elements integrated together;

receiving image data including some number of bits for each pixel;

storing in the data storage array a number of bits for each pixel that is less than the number of bits received for that pixel, thereby creating a stored image;

displaying the stored image on the pixel array by displaying for each pixel a number of bits greater than the number of bits stored for that pixel.

33. A method as defined in claim 32, wherein displaying the stored images includes sequentially displaying different color fields on the same array of picture elements.

34. A method as defined in claim 32, further including:

providing a plurality of storage arrays;

selecting which storage array receives each received image; and

selecting which stored image to display.

35. A method-as defined in claim 32, wherein a portion of the bits of the data stored includes information for more than one pixel.

36. A method as defined in claim 35, wherein luminance information is stored for each pixel and chroma information is stored for groups of pixels.

37. A microdisplay system for displaying image data, comprising:

a microdisplay having an array of pixels switchable between different display states, the microdisplay residing on a semiconductor substrate, each pixel having circuitry in and circuitry operatively associated therewith, the circuitry in and operatively associated with each pixel including a plurality of transistors, there being less than 700 transistors in this circuitry; and

a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format.

38. A microdisplay system as defined in claim 37, wherein there are less than 600 transistors in this circuitry.

39. A microdisplay system as defined in claim 37, wherein there are less than 500 transistors in this circuitry.

40. A microdisplay system as defined in claim 37, wherein there are less than 400 transistors in this circuitry.

41. A microdisplay system as defined in claim 37, wherein there are less than 300 transistors in this circuitry.

42. A microdisplay system as defined in claim 37, wherein there are less than 200 transistors in this circuitry.

43. A microdisplay system as defined in claim 37, wherein there are less than 160 transistors in this circuitry.

44. A microdisplay system as defined in claim 37, wherein there are less than 150 transistors in this circuitry.

45. A microdisplay system as defined in claim 37, wherein there are less than 140 transistors in this circuitry.

46. A microdisplay system as defined in claim 37, wherein there are less than 135 transistors in this circuitry.

47. A microdisplay system for displaying image data, comprising:

a microdisplay having an array of pixels switchable between different display states, the microdisplay residing on a semiconductor substrate, each pixel having a display surface, each pixel having at least one memory register operatively associated therewith that contains information relating to the future display state of the pixel; and

a digital interface device also residing on said semiconductor substrate, the interface device accepting image data in a first format and providing the image data to the pixels of the microdisplay in a second format;

wherein the surface area on the silicon substrate consumed by each pixel and the at least one memory register operatively associated with that pixel is less than 1000 square microns.

48. A microdisplay system as defined in claim 47, wherein the consumed surface area is less than 700 square microns.

49. A microdisplay system as defined in claim 47, wherein the consumed surface area is less than 335 square microns.

50. A microdisplay system as defined in claim 47, wherein the consumed surface area is less than 305 square microns.

51. A microdisplay system as defined in claim 47, wherein the consumed surface area is less than 300 square microns.

52. A microdisplay system as defined in claim 47, wherein at least some of the memory registers operatively associated with each pixel are not physically located within the pixel.

53. A microdisplay system as defined in claim 52, wherein the pixel array lies in a first plane and wherein the memory registers are physically located in a second plane that is generally parallel to and beneath the first plane and wherein the pixel array overlies a majority of the memory registers.

54. A microdisplay system as defined in claim 47, wherein there are spare memory registers available for use by the microdisplay system once it has been determined that one or more memory registers is defective.