Memory command handler for use in an image signal processor having a data driven architecture
First Claim
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1. An image signal processor comprising:
- a local memory to store data; and
a memory command handler including a plurality of memory address generators, each memory address generator to generate a memory address to the local memory and to interpret a command to be performed on the data of the local memory located at the memory address to aid in image processing tasks.
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Abstract
Disclosed is an image signal processor for use in an image processing system. The image signal processor includes a local memory to store data and a memory command handler having a plurality of memory address generators. Each memory address generator generates a memory address to the local memory and interprets a command to perform an operation on the data of the local memory located at the memory address to aid in image processing tasks.
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Citations
38 Claims
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1. An image signal processor comprising:
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a local memory to store data; and
a memory command handler including a plurality of memory address generators, each memory address generator to generate a memory address to the local memory and to interpret a command to be performed on the data of the local memory located at the memory address to aid in image processing tasks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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storing data in a local memory of an image signal processor;
generating a memory address to the local memory utilizing a memory address generator within the image signal processor; and
performing an operation on the data of the local memory located at the memory address utilizing the memory address generator to aid in image processing tasks. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A machine-readable medium having stored thereon instructions, which when executed by a machine, cause the machine to perform the following operations comprising:
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storing data in a local memory of an image signal processor;
generating a memory address to the local memory utilizing a memory address generator within the image signal processor; and
performing an operation on the data of the local memory located at the memory address utilizing the memory address generator to aid in image processing tasks. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. An image processor system comprising:
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a processor coupled to an image processor; and
a double data rate synchronous dynamic random access memory (DDR SDRAM) coupled to the image processor, the image processor including a plurality of image signal processors coupled to one another, each image signal processor including;
a local memory to store data, and a memory command handler including a plurality of memory address generators, each memory address generator to generate a memory address to the local memory and to interpret a command to be performed on the data of the local memory located at the memory address to aid in image processing tasks. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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Specification