Process for sampling the signal delivered by an active pixel of an image sensor, and corresponding sensor
First Claim
1. A process for sampling the signal delivered by an active pixel of an image sensor comprising a phase of storage of the signal in a pair of sampling capacitors comprising two successive respective effective electrical links of the two sampling capacitors with a follower transistor tracking the pixel in the course of the two respective sampling pulses corresponding respectively to two successive different levels of pixel voltage that are applied to a gate of the follower transistor, wherein the process for the storage phase comprises for each sampling capacitor:
- applying to this sampling capacitor a voltage equal to the corresponding pixel voltage minus the gate-source voltage of the follower transistor biased with a predetermined constant bias current for a first predetermined duration so as to obtain for the said sampling capacitor a final state of stable charge;
interrupting the bias current; and
ending the sampling pulse on completion of a second predetermined duration after the said interruption of the current.
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Abstract
The sampling of a pixel signal by a sampling capacitor is effectuated by applying to the sampling capacitor a voltage equal to the corresponding pixel voltage minus the value of the gate-source voltage of a follower transistor biased with a predetermined constant bias current for a first predetermined duration so as to obtain for the sampling capacitor a final state of stable charge. The bias current is then interrupted. Lastly, the end of the sampling pulse occurs on completion of a second predetermined duration after the said interruption of the current.
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Citations
29 Claims
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1. A process for sampling the signal delivered by an active pixel of an image sensor comprising a phase of storage of the signal in a pair of sampling capacitors comprising two successive respective effective electrical links of the two sampling capacitors with a follower transistor tracking the pixel in the course of the two respective sampling pulses corresponding respectively to two successive different levels of pixel voltage that are applied to a gate of the follower transistor, wherein the process for the storage phase comprises for each sampling capacitor:
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applying to this sampling capacitor a voltage equal to the corresponding pixel voltage minus the gate-source voltage of the follower transistor biased with a predetermined constant bias current for a first predetermined duration so as to obtain for the said sampling capacitor a final state of stable charge;
interrupting the bias current; and
ending the sampling pulse on completion of a second predetermined duration after the said interruption of the current. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An image sensor, comprising:
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a matrix of active pixels;
means for processing information delivered by the matrix of active pixels, the processing means comprising;
a pair of sampling capacitors per column of the matrix that are able to be respectively linked electrically to a follower transistor tracking each pixel of the column in the course of two respective sampling pulses corresponding respectively to two successive different levels of pixel voltage that are applied to a gate of the follower transistor;
a current source connected to each column of the matrix, and able to deliver on command to the column a predetermined constant bias current; and
control means operable for each sampling capacitor and in the course of the corresponding sampling pulse to;
energize the column with the bias current for a first predetermined duration so as to obtain for the said sampling capacitor a final state of stable charge;
interrupt the energizing of the column by the bias current; and
end the sampling pulse on completion of a second predetermined duration after the interruption of the current. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A circuit, comprising:
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a pixel sensor;
a transistor coupling the pixel sensor to a bit line;
a first sampling capacitor selectively coupled to the bit line;
a second sampling capacitor selectively coupled to the bit line;
a bias current generator selectively coupled to the bit line;
a control circuit operable to selectively couple the bit line to the first sampling capacitor during a first sample period and selectively couple the bit line to the second sampling capacitor during a second sample period, the control circuit further operable, during each of the first and second sample periods, to selectively couple the bias current generator to the bit line to bias the transistor into a follower configuration. - View Dependent Claims (16, 17, 18)
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19. A method for capacitively sampling a pixel sensor coupled to a bit line through a transistor, comprising:
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initiating a sample period by applying a bias current to the bit line and coupling the bit line to a sensing capacitor;
after a first time period, terminating application of the bias current; and
after a subsequent second time period decoupling the sensing capacitor from the bit line to terminate the sample period. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A circuit, comprising:
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a pixel sensor;
a transistor coupling the pixel sensor to a bit line;
a sampling capacitor selectively coupled to the bit line;
a bias current generator selectively coupled to the bit line;
a control circuit operable to selectively couple the bit line to the sampling capacitor during a sample period, the control circuit further operable to selectively couple the bias current generator during the sample period to the bit line to bias the transistor into a follower configuration. - View Dependent Claims (27, 28, 29)
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Specification