Dual-sided capacitor and method of formation

• US 20040264102A1
• Filed: 07/21/2004
• Published: 12/30/2004
• Est. Priority Date: 08/22/2002
• Status: Active Grant

• Current Assignee: Er-Xuan Ping, Shenlin Chen
• Original Assignee: Er-Xuan Ping, Shenlin Chen
• Inventors: Ping, Er-Xuan, Chen, Shenlin
• Granted Patent: US 7,071,056 B2
• Time in Patent Office: Days
• US Class Current: 361/303
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.

Claims

1-50. -50. (Canceled)

51. A method of forming a capacitor comprising:

forming a hemispherical grained polysilicon layer over a substrate;

subjecting said hemispherical grained polysilicon layer to a cleaning solution to remove impurities from said hemispherical grained polysilicon layer and to obtain a cleaned hemispherical grained polysilicon layer;

forming a native oxide layer over said cleaned hemispherical grained polysilicon layer, said native oxide layer being formed to a thickness of about 5 Angstroms to about 50 Angstroms;

forming an amorphous silicon layer over said native oxide layer;

subjecting said amorphous silicon layer to a seeding treatment;

forming a dielectric layer over at least a portion of an outer side of said cleaned hemispherical grained polysilicon layer and said amorphous silicon layer; and

forming a conductive layer over said dielectric layer.

52. The method of claim 51, wherein said native oxide layer is formed by an in-situ atomic layer deposition process.

53. The method of claim 52, wherein said native oxide layer is formed by employing a silicon source precursor and an oxygen source.

54. The method of claim 51, wherein said native oxide layer is formed by an ex-situ atomic layer deposition process.

55. The method of claim 54, wherein said native oxide layer is formed by employing a silicon source precursor and an oxygen source.

56. The method of claim 51, wherein said native oxide layer is thermally grown at a temperature of less than about 900°

C. for about 1 second to about 10 minutes.

57. The method of claim 51 further comprising the step of annealing said amorphous silicon layer subsequent to said step of subjecting said amorphous silicon layer to a seeding treatment.

58. The method of claim 57, wherein a hemispherical grained polysilicon layer is formed as a result of the step of annealing said amorphous silicon layer, said hemispherical grained polysilicon layer having grains formed to a thickness of about 100 Angstroms to about 500 Angstroms.

59. The method of claim 58, wherein said step of annealing said amorphous silicon layer is conducted at a temperature of about 600°

C. to about 700°

C.

60. A method of forming a capacitor comprising:

forming a hemispherical grained polysilicon layer over a substrate;

forming a native oxide layer over said hemispherical grained polysilicon layer by an in-situ atomic layer deposition employing a silicon source precursor and an oxygen source;

forming an amorphous silicon layer over said native oxide layer;

forming a dielectric layer over at least a portion of an outer side of said hemispherical grained polysilicon layer and said amorphous silicon layer; and

forming a conductive layer over said dielectric layer.

61. The method of claim 60 further comprising the step of subjecting said amorphous silicon layer to a seeding treatment.

62. The method of claim 61 further comprising the step of annealing said amorphous silicon layer subsequent to said step of subjecting said amorphous silicon layer to a seeding treatment.

63. The method of claim 62, wherein a hemispherical grained polysilicon layer is formed as a result of the step of annealing said amorphous silicon layer, said hemispherical grained polysilicon layer having grains formed to a thickness of about 100 Angstroms to about 500 Angstroms.

64. The method of claim 63, wherein said step of annealing said amorphous silicon layer is conducted at a temperature of about 600°

C. to about 700°

C.

65. A method of forming a capacitor comprising:

forming a hemispherical grained polysilicon layer over a substrate;

forming a native oxide layer over said hemispherical grained polysilicon layer by an ex-situ atomic layer deposition employing a silicon source precursor and an oxygen source;

forming an amorphous silicon layer over said native oxide layer;

forming a dielectric layer over at least a portion of an outer side of said hemispherical grained polysilicon layer and said amorphous silicon layer; and

forming a conductive layer over said dielectric layer.

66. The method of claim 65 further comprising the step of subjecting said amorphous silicon layer to a seeding treatment.

67. The method of claim 66 further comprising the step of annealing said amorphous silicon layer subsequent to said step of subjecting said amorphous silicon layer to a seeding treatment.

68. The method of claim 67, wherein a hemispherical grained polysilicon layer is formed as a result of the step of annealing said amorphous silicon layer, said hemispherical grained polysilicon layer having grains formed to a thickness of about 100 Angstroms to about 500 Angstroms.

69. The method of claim 68, wherein said step of annealing said amorphous silicon layer is conducted at a temperature of about 600°

C. to about 700°

C.

70. A method of forming a capacitor comprising:

forming a hemispherical grained polysilicon layer over a substrate;

forming a native oxide layer over said hemispherical grained polysilicon layer by thermal growth at a temperature of less than about 900°

C. for about 1 second to about 10 minutes;

forming an amorphous silicon layer over said native oxide layer;

forming a dielectric layer over at least a portion of an outer side of said hemispherical grained polysilicon layer and said amorphous silicon layer; and

forming a conductive layer over said dielectric layer.

71. The method of claim 70 further comprising the step of subjecting said amorphous silicon layer to a seeding treatment.

72. The method of claim 71 further comprising the step of annealing said amorphous silicon layer subsequent to said step of subjecting said amorphous silicon layer to a seeding treatment.

73. The method of claim 72, wherein a hemispherical grained polysilicon layer is formed as a result of the step of annealing said amorphous silicon layer, said hemispherical grained polysilicon layer having grains formed to a thickness of about 100 Angstroms to about 500 Angstroms.

74. The method of claim 73, wherein said step of annealing said amorphous silicon layer is conducted at a temperature of about 600°

C. to about 700°

C.

75. A method of reducing the diffusivity of silicon atoms of a lower capacitor electrode, comprising:

providing a doped polysilicon layer in an opening formed within a semiconductor substrate, said doped polysilicon layer comprising hemispherical grained polysilicon grains having a first thickness;

providing a native oxide layer over said doped polysilicon layer; and

providing a layer of hemispherical grained polysilicon over said native oxide layer, said layer of hemispherical grained polysilicon comprising grains of a second thickness, wherein said second thickness is greater than said first thickness.

76. The method of claim 75 further comprising:

forming a dielectric layer over at least a portion of said doped polysilicon layer and said layer of hemispherical grained polysilicon; and

forming a conductive layer over said dielectric layer.

77. The method of claim 75, wherein said first thickness is of about 10 Angstroms to about 50 Angstroms.

78. The method of claim 75, wherein said second thickness is of about 100 Angstroms to about 500 Angstroms.

79. The method of claim 75, wherein said native oxide layer is formed by an in-situ oxidation of said doped polysilicon layer.

80. The method of claim 79, wherein said native oxide layer is formed by an in-situ oxidation of said doped polysilicon layer under a low partial pressure.

81. The method of claim 80, wherein said low partial pressure is of about 10-6 Torr.

82. The method of claim 81, wherein said native oxide layer is formed by an in-situ oxidation of said doped polysilicon layer under a low partial pressure of about 10-6 Torr and for about 1-5 minutes.

83. The method of claim 75, wherein said native oxide layer is formed by atomic layer deposition.