Random number generator with ring oscillation circuit

• US 20040264233A1
• Filed: 06/24/2004
• Published: 12/30/2004
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas System Design, Co., Ltd. (Renesas Electronics Corporation), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamaguchi, Atsuo, Fukushima, Kazuhiko
• Granted Patent: US 7,424,500 B2
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G11C 2029/3602 Pattern generator
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters

Abstract

A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop'"'"'s delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Claims

1. A random number generator comprising:

a plurality of delay circuits connected in a loop;

a pulse generation circuit generating in said loop a pulse signal having a pulse of a width shorter than a total delay time of said plurality of delay circuits; and

a counter connected to an output node of a delay circuit of said plurality of delay circuits to count how many times said pulse signal passes through said output node, and output a true random number data signal based on a value counted by said counter.

2. The random number generator of claim 1, wherein:

one of said plurality of delay circuits includes a logic gate circuit;

said logic gate circuit has one input node receiving a signal output from said delay circuit of a preceding stage and has an output node connected to an input node of said delay circuit of a subsequent stage; and

said pulse generation circuit applies a start signal to said logic gate circuit at the other input node to generate said pulse signal.

3. The random number generator of claim 2, wherein:

said logic gate circuit is an exclusive OR gate circuit; and

each of said delay circuits other than said one delay circuit is an inverter.

4. The random number generator of claim 2, wherein:

said logic gate circuit is an NAND gate circuit; and

each of said delay circuits other than said one delay circuit is an inverter.

5. The random number generator of claim 1, wherein:

said plurality of delay circuits each include a logic gate circuit, each having one input node receiving a signal output from said logic gate circuit of a preceding stage; and

said pulse generation circuit applies a start signal to said logic gate circuit at the other input node to generate said pulse signal.

6. The random number generator of claim 5, wherein said logic gate circuit is an NAND gate circuit.

7. The random number generator of claim 1, wherein:

said delay circuits connected in said loop are variable in number; and

said pulse generation circuit generates said pulse signal by changing in number said delay circuits connected in said loop.

8. The random number generator of claim 7, wherein for a start signal having a first potential said pulse generation circuit connects a first number of delay circuits in a loop to form a ring oscillator and for said start signal having a second potential said pulse generation circuit connects a second number of delay circuits in a loop to form an attenuation circuit.

9. The random number generator of claim 7, wherein for a start signal having a first potential said pulse generation circuit connects a first number of delay circuits in a loop to form a first ring oscillator and for said start signal having a second potential said pulse generation circuit connects a second number of delay circuits in a loop to form a second ring oscillator.

10. The random number generator of claim 1, wherein said plurality of delay circuits include first and second inverters alternately, said first inverter outputting a signal transitioning from first to second potentials with a first delay time, and a signal transitioning from said second to first potentials with a second delay time, said second inverter outputting a signal transitioning from first to second potentials with said second delay time, and a signal transitioning from said second to first potentials with said first delay time.

11. The random number generator of claim 1, further comprising:

a plurality of counters connected to different delay circuits, respectively, at their respective output nodes; and

a first adder circuit adding together true random number data signals output from said plurality of counters.

12. The random number generator of claim 11, wherein an odd number of said counters are arranged.

13. The random number generator of claim 11, wherein said delay circuits corresponding to said plurality of counters, respectively, output signals having identical logic levels.

14. The random number generator of claim 11, further comprising a select circuit selecting any one of said plurality of counters to apply only the selected circuit'"'"'s output signal to said first adder circuit.

15. The random number generator of claim 11, further comprising:

a pseudo random number generation circuit outputting a pseudo random number data signal allowing 0 and 1 to appear equally frequently; and

a second adder circuit receiving said true random number data signal from said first adder circuit and said pseudo random number data signal from said pseudo random number generation circuit to add said signals together to output a random number data signal.

16. The random number generator of claim 15, further comprising a random number storage circuit receiving said random number data signal from said second adder circuit to sequentially store said random number data signal to generate a random number value including a random number data signal of a predetermined bit count.

17. The random number generator of claim 16, further comprising:

a bit counter counting a number of bits of said random number data signal stored in said random number storage circuit; and

a control circuit reading said random number value from said random number storage circuit in response to said bit counter counting a predetermined bit count.

18. The random number generator of claim 17, wherein an operation performed to generate a random number is stopped for a predetermined period of time after said bit counter counts said predetermined bit count, and said control circuit reads said random number value from said random number storage circuit for said predetermined period of time.

19. The random number generator of claim 17, said bit counter causing a control signal to transition from a first potential to a second potential in response to said bit counter having counted said predetermined bit count, the random number generator further comprising a switch circuit operating in a test to apply said control signal, rather than said random number data signal, to said random number storage circuit.