Apparatus and method for testing memory cards

• US 20040267481A1
• Filed: 05/19/2004
• Published: 12/30/2004
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Resnick, David R., Bethard, Roger A., Snyder, Van L., Schwoerer, Gerald A., Grossmeier, Alan M., Marquardt, Kelly J., Steinberger, Michael L.
• Granted Patent: US 7,184,916 B2
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/4002 Comparison of products, i.e. test results of chips or with golden chip
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair

Abstract

A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card'"'"'s functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card'"'"'s functions.

Claims

1. A first circuit for use with a first memory card, the card having a plurality of memory chips, the first circuit comprising:

a memory-chip interface;

a high-speed external interface connected to receive write data for sending to the memory-chip interface, and to transmit data obtained from the memory-chip interface; and

a test engine configured to control the high-speed interface and/or the memory chips and to provide testing functions for this first card and of a second substantially identical circuit on a second memory card.

2. The first circuit of claim 1, further comprising one or more memory controllers, each one of the one or more memory controllers connected to control at least a subset of the plurality of memory chips through the memory-chip interface.

3. The first circuit of claim 2, further comprising one or more caches, each one of the one or more caches operatively coupled to a corresponding one of the memory controllers.

4. The first circuit of claim 2, further comprising one or more caches, each one of the one or more caches operatively coupled to two or more of the memory controllers.

5. The first circuit of claim 3, wherein the high-speed external card interface further comprises:

a crossbar switch; and

one or more SerDes ports, each one of the one or more SerDes ports connectable through the crossbar switch to a plurality of the caches.

6. The first circuit of claim 1, further comprising:

a control interface, the control interface configured to initialize, control, configure, and interact with all internal functions and to program the test engine and to initialize, control testing, and observe test results and sequences.

7. A system for using a first memory card to test a second memory card, the system comprising:

a test fixture having a first interface connectable to the first memory card and a second interface connectable to the second memory card, such that at least some inputs from the first interface are connected to corresponding outputs of the second interface, and at least some outputs from the first interface are connected to corresponding inputs of the second interface; and

a test controller operable to send configuration data to the first interface to cause a testing function to be performed when suitable first and second memory cards are connected to the fixture.

8. The system of claim 7, wherein the first interface connects a high-speed SerDes port of the first memory card to a corresponding SerDes port of the second card.

9. The system of claim 7, wherein the test controller receives test results from the first memory card indicative of functionality of the second memory card.

10. The system of claim 7, wherein the test controller includes an interface to send and receive data from respective control interface ports on the first memory card and the second memory card.

11. The system of claim 7, wherein the test controller is operable to configure the second memory card to each one of a plurality of different operation modes.

12. The system of claim 7, further including a test controller connection to both the first and second memory cards.

13. A method for testing memory cards, the method comprising:

connecting a plurality of interface lines of a first memory card to corresponding complementary interface lines of a second memory card;

configuring the first memory card to be operable to perform testing functions;

configuring the second memory card to be operable to perform normal read and write operations; and

testing the second memory card under the control of the first memory card.

14. The method of claim 13, wherein the configuring of the first memory card includes loading microcode into the first memory card.

15. A computer-readable medium having instructions stored thereon, for causing a suitably programmed information-processing system to execute a method comprising:

connecting a plurality of interface lines of a first memory card to corresponding complementary interface lines of a second memory card;

configuring the first memory card to be operable to perform testing functions;

configuring the second memory card to be operable to perform normal read and write operations; and

testing the second memory card under the control of the first memory card.

16. A first memory card comprising:

a plurality of memory chips;

one or more high-speed external card interfaces, including a first interface and a second interface, each connected to write and read data to and from the memory chips; and

a test engine configured to control the first high-speed interface and the memory chips in order to provide testing functions to the second high-speed interface.

17. The first memory card of claim 16, wherein the test engine is operable to generate requests that look like and perform as normal requests to the card.

18. The first memory card of claim 16, wherein the test engine includes internal paths that enable the test engine to send requests to and receive results from a plurality of internal chip functions.

19. The first memory card of claim 16, further comprising circuitry that allows results to return in a different order than the order in which they were generated.

20. The first memory card of claim 16, further comprising a microcode memory that stores code that controls at least some functions of the test engine.

21. A computer system comprising:

a first processing unit; and

the first memory card of claim 16 operatively coupled to the first processing unit.

22. The computer system of claim 21, further comprising a second memory card substantially identical to the first memory card, and operatively coupled to the first processing unit.

23. The computer system of claim 22, wherein at least one interface port of the first memory card is complementarily connected to a respective interface port of the second memory card, and wherein the first processing unit is configured to load configuration information into the first memory card to cause the first memory card to perform test functions to the second memory card, the first processing unit also configured to receive test results.

24. The computer system of claim 22, wherein the first processing unit is configured to load configuration information into the first memory card and the second memory card to cause the first memory card and second memory card to perform normal read and write operations.

25. The computer system of claim 22, further comprising:

a second processing unit;

a third memory card substantially identical to the first memory card, and operatively coupled to the second processing unit; and

a fourth memory card substantially identical to the first memory card, and operatively coupled to the second processing unit.

26. A first memory card comprising:

a plurality of memory chips;

a high-speed external card interface connected to write and read data to and from the memory chips; and

a test engine configured to control the high-speed interface and/or the memory chips in order to provide testing functions to a second substantially identical memory card.

27. The first memory card of claim 26, further comprising:

one or more memory controllers, each one of the one or more memory controllers connected to control a subset of the plurality of memory chips.

28. The first memory card of claim 27, further comprising:

one or more caches, each one of the one or more caches operatively coupled to a corresponding one of the memory controllers.

29. The first memory card of claim 28, wherein the high-speed external card interface further comprises:

a crossbar switch; and

one or more SerDes ports, each one of the one or more SerDes ports connectable through the crossbar switch to a plurality of the caches.

30. The first memory card of claim 26, further comprising:

a control interface, the control interface configured to program the test engine and to initialize, control, and observe test sequences.

31. A memory-support circuit comprising:

a system interface;

a memory interface operable to generate read and write operations to a memory, wherein the circuit operates to provide data from the memory interface into the system interface; and

a test engine operatively coupled to control the system interface and the memory interface in order to provide programmably configurable testing functions.

32. The circuit of claim 31, further comprising a control interface, wherein testing configuration information is loadable through the control interface into the test engine to provide the programmably configurable testing functions.

33. The circuit of claim 31, further comprising a cache operatively coupled to the memory interface and the system interface to provide cached data to the system interface.

34. The circuit of claim 31, wherein the test engine includes:

a test-generation function; and

a test-result-checking function, wherein results can be returned and checked in an order different than the order in which they were generated.

35. An integrated-circuit chip comprising:

an input-output port; and

a test engine operatively coupled to control the input/output port such that functionality of the input/output port can be tested by connecting the input/output port to a similar port of another chip and sending test commands to and receiving test results from the other chip'"'"'s port.

36. The chip of claim 35, wherein the testing can be performed without regard to the electrical and architectural implementation of the ports.

37. The chip of claim 35, further comprising a memory interface operable to generate read and write operations to a memory, wherein the circuit operates to provide data from the memory interface into the input/output port.

38. The chip of claim 35, further comprising a control interface, wherein testing configuration information is loadable through the control interface into the test engine to provide testing functions.

39. The chip of claim 35, further comprising a cache operatively coupled to the memory interface and the input/output port to provide cached data to the input/output port.

40. The chip of claim 35, further comprising functional logic on the chip;

wherein use of the test engine is independent of operation of the functional logic.

41. The chip of claim 37, further comprising functional logic on the chip;

wherein use of the test engine is independent of and tests operation of the functional logic.

42. The chip of claim 41, wherein the test engine generates a plurality of tests in order that two or more simultaneous functions of the functional logic are tested at the same time.

43. The chip of claim 37, wherein the test engine provides a function that is used in normal operation of the chip.

44. A system for testing a first memory card, the system comprising:

a test fixture having a first interface connectable to the first memory card, such that at least some inputs of the first interface are connected to corresponding outputs of the first interface; and

a test controller operable to send test configuration data to the first interface to cause a testing function to be performed by the first memory card when connected to the fixture.

45. The system of claim 44, wherein the first interface connects one SerDes port of the first memory card to another SerDes port of the first memory card.

46. The system of claim 44, wherein the test controller receives test results from the first memory card indicative of functionality of the first memory card.

47. The system of claim 44, wherein the test controller includes an interface to send and receive data from a control interface ports on the first memory card.

48. The system of claim 44, wherein the test controller is operable to configure the first memory card to each one of a plurality of different operation modes.