Pass through circuit for reduced memory latency in a multiprocessor system
First Claim
1. A multiprocessor system, comprising:
- a set of processors;
a system board having a set of sockets, each socket suitable for receiving one of the set of processors wherein the number of sockets in the set of sockets exceeds the number of processors in the set of processors;
a set of interconnects providing point-to-point links between at least some of the sockets; and
a pass through device occupying one of the set of sockets, wherein the pass through device connects a first interconnect link connected to the socket and a second interconnect link connected to the socket such that the first and second interconnect links form the functional equivalent of a single interconnect link.
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Abstract
A technique and mechanism for reducing memory latency asymmetry in a multiprocessor system by replacing one (or more) processors with a bypass or pass-through device. Using the pass-through mechanism, the reduced number of processors in the system enables all of the remaining processors to connect to each other directly using the interconnect links. The reduction in processor count improves symmetry and reduces overall latency thereby potentially improving performance of certain applications despite having fewer processors. In one specific implementation, the pass through device is used to connect two HyperTransport links together where each of the links is connected to a processor at the other end.
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Citations
22 Claims
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1. A multiprocessor system, comprising:
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a set of processors;
a system board having a set of sockets, each socket suitable for receiving one of the set of processors wherein the number of sockets in the set of sockets exceeds the number of processors in the set of processors;
a set of interconnects providing point-to-point links between at least some of the sockets; and
a pass through device occupying one of the set of sockets, wherein the pass through device connects a first interconnect link connected to the socket and a second interconnect link connected to the socket such that the first and second interconnect links form the functional equivalent of a single interconnect link. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A pass through device for use with a data processing system, comprising:
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a first set of pins configured to connect to a first set of signals on the system board wherein the first set of signals correspond to a first instance of an inter-chip link;
a second set of pins configured to connect to a second set of signals on the system board wherein the second set of signals correspond to a second instance of the inter-chip link; and
a set of wires connecting the first set of pins directly to the second pins wherein the first instance of the inter-chip link is connected to the second instance of the inter-chip link when the pass through device is inserted in the system board. - View Dependent Claims (11, 12, 13, 14)
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15. A data processing system, comprising:
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a system board including a set of sockets suitable for receiving a corresponding set of processors and further including a first instance of an inter-chip link connecting a first socket of the set of sockets to a second socket and a second instance of an inter-chip link connecting the second socket to a third socket;
a first processor inserted in the first processor socket;
a second processor inserted in the third processor socket; and
a pass through device inserted in the second socket, wherein the pass through device connects the first instance of the inter-chip link to the second instance of the inter-chip wherein the first processor is directly connected to the second processor via the first and second instances of the inter-chip link. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification