Efficient memory controller

• US 20040268030A1
• Filed: 05/12/2004
• Published: 12/30/2004
• Est. Priority Date: 06/30/2003
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Cheung, Frank Nam Go
• Granted Patent: US 7,370,169 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20

Abstract

An efficient memory controller. The controller includes a first mechanism for associating one or more input command sequences with one or more corresponding values. A second mechanism selectively sequences one of the one or more command sequences to a memory in response to a signal. A third mechanism compares each of the one or more values to a state of the second mechanism and provides the signal in response thereto. In a specific embodiment, the one or more corresponding values are execution time code values, and the second mechanism includes a sequencer state machine that provides the state of the second mechanism as a sequencer time code. In the specific embodiment, a compare module compares the sequencer time code to a time code associated with a next available command sequence and execution time code pair and provides the signal in response thereto.

Claims

1. An efficient memory controller comprising:

first means for associating one or more input command sequences with one or more corresponding values;

second means for selectively sequencing one of said one or more command sequences to a memory in response to a signal; and

third means for comparing each of said one or more values to a state of said second means and providing said signal in response thereto.

2. The controller of claim 1 wherein said one or more corresponding values are execution time code values.

3. The controller of claim 2 wherein said second means includes a sequencer state machine, and wherein said sequencer state machine provides said state as a sequencer time code.

4. The controller of claim 3 wherein said first means includes means for choosing said execution time code values in accordance with said sequencer time code.

5. The controller of claim 3 wherein said third means includes a compare module for comparing said sequencer time code to an execution time code associated with a next available command sequence and execution time code pair and providing said signal in response thereto.

6. The controller of claim 5 wherein said compare module is incorporated within a sequencer that includes said sequencer state machine.

7. The controller of claim 6 wherein said first means includes a decoding module included in an instruction decoder that further includes a generator for providing said next available command sequence and execution time code pair.

8. The controller of claim 7 wherein said decoding module and said compare module receive sequencer state time code data as feedback from said sequencer state machine.

9. The controller of claim 8 wherein said instruction decoder further includes a memory state tracking module in communication with said decoding module.

10. The controller of claim 7 wherein said first means is implemented via said instruction decoder, and wherein said second means and said third means are implemented via said sequencer.

11. The controller of claim 10 wherein said instruction decoder and said sequencer are connected in a pipelined master-slave configuration, said sequencer acting as the slave to said instruction decoder.

12. The controller of claim 11 wherein said memory is a Synchronous Dynamic Random Access Memory (SDRAM), an Enhanced SDRAM (ESDRAM), a Virtual Channel Memory (VCM), or a variant thereof.

13. The controller of claim 3 wherein said controller is part of an overall system that further includes a memory data arbitrator that receives control input from said sequencer state machine and selectively provides data to or accepts data from said memory in response thereto, said memory data arbitrator employing one or more First In First Out (FIFO) buffers to facilitate data flow to and from memory.

14. The system of claim 13 further including a computation system for selectively providing said input command sequences to said first means and for selectively providing data to and accepting data from said memory data arbitrator as needed to meet the needs of a given application.

15. The system of claim 14 further including a command arbitrator that receives commands from said computation system and selectively provides corresponding commands to said first means.

16. The system of claim 15 wherein said command arbitrator includes a priority encoder for prioritizing and ordering said corresponding commands before said corresponding commands are transferred, in order, to said first means, said priority encoder providing a command-start signal to said memory controller.

17. An efficient memory managing system comprising:

first means for receiving one or more input command sequences;

second means for associating said one or more input command sequences with one or more corresponding values;

third means for comparing each of said one or more values to a sequencing state and providing a signal in response thereto; and

fourth means for selectively sequencing a preferred one of said one or more command sequences to a memory in response to said signal.

18. The controller of claim 17 wherein said one or more corresponding values include execution time codes.

19. The controller of claim 18 wherein said sequencing state is represented by a sequencer state time code that is input to said second means.

20. The controller of claim 19 wherein said second means includes a command and time code generator for assigning an execution time code to said preferred one of said one or more command sequences to be processed next.

21. The controller of claim 20 wherein said system includes a priority encoder for selecting said preferred one of said one or more command sequences.

22. The controller of claim 21 wherein said third means includes means for determining if said execution time code is less than or equal to said sequencer state time code and providing an enable signal in response thereto.

23. The controller of claim 22 wherein said fourth means includes a sequencer state machine for sequencing said preferred one of said one or more command sequences in response to said enable signal.

24. The controller of claim 23 wherein said sequencer state machine provides a command-sent signal to said priority encoder upon sequencing said preferred one of said one or more command sequences to memory.

25. The controller of claim 24 wherein said priority encoder selectively provides a command-start signal to said command and time code generator, and wherein said command and time code generator selectively provides a sequencer-start command to said sequencer state machine in response thereto.

26. The controller of claim 25 wherein said system further includes means for indicating to said command and time code generator when a command is waiting to be sequenced, and includes means for indicating when said command and time code generator has forwarded a command to said sequencer state machine.

27. The controller of claim 23 wherein said sequencer state machine is configured to increment said sequencer state time code as a command is being sequenced.

28. The controller of claim 21 wherein said third means includes means for determining if said execution time code is less than, less than or equal, greater than, or greater than or equal to said sequencer state time code and selectively increasing or decreasing said sequencer state time code as a command sequence is being serviced.

29. A computer with optimized memory management and control comprising:

a memory;

a computation system that generates memory requests;

a memory managing section that selectively controls data flow between said memory and said computation system based on memory requests and prioritizes said memory requests, providing prioritized requests in response thereto; and

a memory controller that selectively services said prioritized requests at times determined by a current state of command servicing operations and an execution code assigned to each of said prioritized requests.

30. The computer of claim 29 wherein said memory controller includes an instruction decoder and a sequencer in a master-slave configuration, and wherein said current state of command servicing operations is represented by a sequencer state time code that is provided as feedback from said sequencer to said instruction decoder, said instruction decoder assigning said execution code to each prioritized request, and said sequencer comparing said execution code to said sequencer state time code to determine when a prioritized request should be serviced by said sequencer.

31. A method for improving memory bandwidth comprising:

receiving and formatting memory requests and memory state variables and providing formatted information in response thereto;

employing said formatted information to assign execution time codes to received memory requests;

comparing said execution time codes with sequencer time codes, said sequencer time codes corresponding to states of a sequencer designed to sequence said memory requests;

selectively servicing said memory requests based on the results of said comparing step;

updating the sequencer time codes as said memory requests are being processed; and

returning to said step of receiving as needed while said memory requests are being serviced by said sequencer.

32. A method for facilitating memory command control comprising:

associating one or more input command sequences with one or more corresponding values;

selectively sequencing one of said one or more command sequences to a memory in response to a signal; and

comparing each of said one or more values to a state of said second means and providing said signal in response thereto.