Cache operation with non-cache memory

• US 20040268049A1
• Filed: 05/24/2004
• Published: 12/30/2004
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: Malikie Innovations Limited (Key Patent Innovations Limited)
• Original Assignee: Research In Motion Limited (Blackberry Limited)
• Inventors: Madter, Richard C.
• Granted Patent: US 7,159,076 B2
• Time in Patent Office: Days
• US Class Current: 711/133
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

A system and method are provided for using cache memory when reading data from system memory particularly when the primary memory could include memory types other than fast read-write memory. Also, a system and method are provided for using cache memory when writing data to system memory particularly when the primary memory could include memory types other than fast read-write memory.

Claims

1. A method for writing data to non-cache memory in a system having cache memory comprising the following steps:

initiating a write operation so that data can be written to a location in non-cache memory;

accessing a cache configuration register to obtain information for use in identifying the memory type of the non-cache memory location to which the write operation is directed;

determining that the non-cache memory location to which the write operation is directed does not comprise a fast read-write memory type;

identifying a line in system cache memory whose contents mirrors the content of the non-cache memory location to which the write operation is directed;

determining that the system has designated the line in system cache memory as being valid;

invalidating the line in system cache memory; and

writing data to the non-cache memory.

2. A method for writing data to non-cache memory in a system having cache memory comprising the following steps:

initiating a write operation so that data can be written to a location in non-cache memory;

obtaining information for use in identifying the memory type of the non-cache memory location to which the write operation is directed;

determining whether the non-cache memory location to which the write operation is directed comprises a fast read-write memory type;

identifying whether a line in system cache memory exists whose contents mirrors the content of the non-cache memory location to which the write operation is directed if the non-cache memory location to which the write operation is directed does not comprise a fast read-write memory type;

determining whether the system has designated the line in system cache memory as being valid if the line is identified;

invalidating the line in system cache memory if the line is identified and if the system had designated the line as being valid; and

writing data to the non-cache memory.

3. The method according to claim 2 wherein the obtaining step comprises the step of accessing a cache configuration register to obtain the information.

4. The method according to claim 2 wherein the non-cache memory comprises a fast read-write memory type.

5. The method according to claim 4 further comprising the step of writing the data to a line in the cache memory.

6. The method according to claim 2 wherein the non-cache memory does not comprise a fast read-write memory type.

7. The method according to claim 6 wherein a line in system cache memory does not exist whose contents mirrors the content of the non-cache memory location to which the write operation is directed.

8. The method according to claim 6 wherein a line in system cache memory exists whose contents mirrors the content of the non-cache memory location to which the write operation is directed.

9. The method according to claim 8 wherein the line in system cache memory has not been designated as being valid.

10. The method according to claim 8 wherein the line in system cache memory has been designated as being valid.

11. The method according to claim 2 wherein the step of invalidating the line of cache memory includes the step of setting the value of a valid bit within the line of cache memory to 0.

12. The method according to claim 2 wherein the step of invalidating the line of cache memory includes the step assigning a non-occurring address tag to the line of cache memory.

13. The method according to claim 2 wherein the non-cache memory is a flash memory.

14. The method according to claim 2 wherein the non-cache memory is an EEPROM.

15. A method for reading data from non-cache memory in a system having cache memory comprising the following steps:

initiating a read operation;

obtaining memory type information for use in identifying the memory type of the non-cache memory location to which the read operation is directed

determining whether the non-cache memory is a fast read-write memory type;

determining whether the cache is to be bypassed if the non-cache memory is not a fast read-write memory type;

determining whether the desired data is in the cache if the cache is not to be bypassed;

reading the desired data from the cache if it is determined that the desired data is in the cache; and

reading the desired data from the non-cache memory if it is determined that the desired data is not in the cache or if it is determined that the cache is to be bypassed.

16. The method according to claim 15 wherein the obtaining memory type information step comprises the step of accessing a cache configuration register to obtain the memory type information.

17. The method according to claim 15 wherein the step of determining whether the cache is to be bypassed comprises the step of obtaining bypass state setting information that indicates whether the cache memory is to be bypassed for that non-cache memory location.

18. The method according to claim 17 wherein the step of obtaining bypass state setting information comprises the step of accessing a cache configuration register to obtain the bypass state setting information.

19. The method according to claim 15 wherein the non-cache memory is not a fast read-write memory type and the requested data is read from the cache memory.

20. The method according to claim 15 wherein the non-cache memory is a fast read-write memory type and the requested data is read from the cache memory.

21. The method according to claim 15 wherein the non-cache memory is not a fast read-write memory type and the requested data is read from the non-cache memory.

22. The method according to claim 15 wherein the non-cache memory is a fast read-write memory type and the requested data is read from the non-cache memory.

23. The method according to any of claims 21 or 22 wherein the method further comprises the following steps:

writing the data to a line of the cache memory after reading the data from the primary memory;

reading information in addition to the requested data contained in a line of the primary memory that contained the requested data;

writing the additional information to the line of the cache memory; and

marking the line of the cache memory as valid.

24. The method according to claim 15 wherein the non-cache memory is in a status or configuration parameter read mode.

25. The method according to claim 15 wherein the non-cache memory is a flash memory.

26. The method according to claim 15 wherein the non-cache memory is an EEPROM.

27. An electronic system comprising:

a cache memory subsystem;

a non-cache memory subsystem; and

a logic device that is operative to read data from the cache memory subsystem and from the non-cache memory subsystem, wherein the logic device is operative to determine if a memory location in the non-cache memory subsystem that contains desired data is fast read-write memory, is operative to determine if the cache memory subsystem is to be bypassed during a read operation if the memory location in the non-cache memory subsystem that contains the desired data is not a fast read-write memory, is operative to determine whether the desired data is in the cache memory subsystem if the cache memory subsystem is not to be bypassed, is operative to read the desired data from the cache memory subsystem if it is determined that the desired data is in the cache, and is operative to read the desired data from the primary non-cache memory subsystem if it is determined that the desired data is not in the cache memory subsystem or if it is determined that the cache memory subsystem is to be bypassed.

28. The system according to claim 27 wherein the non-cache memory subsystem comprises flash memory.

29. The system according to claim 27 wherein the non-cache memory subsystem comprises electronically erasable programmable read only memory (“

EEPROM”

).

30. The system according to claim 27 wherein the non-cache memory subsystem comprises dynamic random access memory (“

DRAM”

).

31. The system according to claim 27 wherein the non-cache memory subsystem comprises one or more or any combination of one or more memory types from the group consisting of flash memory, EEPROM, DRAM, SRAM, MRAM, EPROM, ROM, and CCD memory.

32. An electronic system comprising:

a cache memory subsystem;

a non-cache memory subsystem; and

a logic device that is operative to write data to the cache memory subsystem and to the non-cache memory subsystem, wherein the logic device is operative to determine if the non-cache memory location to which the write operation is directed comprises fast read-write memory, to determine whether a line in the cache memory subsystem exists whose contents mirrors the content of the location in the non-cache memory subsystem to which the write operation is directed if the location in the non-cache memory subsystem to which the write operation is directed does not comprise fast read-write memory, to determine whether the system has designated the line in the cache memory subsystem as being valid if the line exists, and to invalidate the line in system cache memory if the line exists and if the system had designated the line as being valid.

33. The system according to claim 32 wherein the non-cache memory subsystem comprises flash memory.

34. The system according to claim 32 wherein the non-cache memory subsystem comprises electronically erasable programmable read only memory (“

EEPROM”

).

35. The system according to claim 32 wherein the non-cache memory subsystem comprises dynamic random access memory (“

DRAM”

).

36. The system according to claim 32 wherein the non-cache memory subsystem comprises one or more or any combination of one or more memory types from the group consisting of flash memory, EEPROM, DRAM, SRAM, MRAM, EPROM, ROM, and CCD memory.