Controlling memory access devices in a data driven architecture mesh array

• US 20040268088A1
• Filed: 06/30/2003
• Published: 12/30/2004
• Est. Priority Date: 06/30/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lippincott, Louis A., Cheah, Chin Hong
• Granted Patent: US 7,827,386 B2
• Time in Patent Office: Days
• US Class Current: 712/25
• CPC Class Codes: G06F 9/4494 data driven

Abstract

A first set of instructions and incoming data are provided to a first processing unit of a data driven processor, to operate upon the incoming data. The first processing unit, in response to recognizing that the first set of instructions will require either reading from or writing to external memory, sets up a logical channel between a second processing unit of the processor and the external memory, to transfer additional data between the external memory and the second processing unit. This capability may be implemented by the addition of a control port, separate from data ports, to the first processing unit, where the control port allows the first processing unit to write addressing information and mode information (including the location of the additional data) for reading or writing the additional data via a memory access unit data channel of the processor.

Claims

1. A data driven processing method, comprising:

providing a first set of instructions and incoming data to a first processing unit, of a data driven processor, to operate upon said incoming data;

configuring a data path for transferring data between a second processing unit of the data driven processor and external memory; and

the first processing unit, in response to recognizing that the first set of instructions will require one of reading from and writing to external memory, provides addressing information to a memory access unit of the processor to enable the transfer of additional data between the external memory and the second processing unit via said data path.

2. The method of claim 1 wherein the first processing unit recognizes an image processing motion vector in said first set of instructions, and said additional data is to be written to the external memory and includes a macro block generated by the second processing unit based on the motion vector.

3. The method of claim 1 wherein the data path is configured by an external host controller.

4. The method of claim 1 further comprising:

the first processing unit providing an indication to the memory access unit of whether the transfer is one of a read and a write.

5. A data processor comprising:

a first direct memory access (DMA) unit; and

a plurality of processing units each having a plurality of data ports, the data ports being coupled to each other and programmable to allow data flow from any one of the processing units to another and from any one of the processing units to the DMA unit,

wherein one of the processing units has a control port from which it is to send information to the DMA unit about setting up a DMA channel through which one of data to be consumed and result data by one of the processing units is transferred.

6. The processor of claim 5 further comprising:

memory interface circuitry, wherein the DMA unit is to access external memory via the memory interface circuitry.

7. The processor of claim 6 wherein the memory interface circuitry is on-chip with the DMA unit, the plurality of processing units, and the host interface.

8. The processor of claim 6 wherein the memory interface circuitry is designed to interface with external memory that is dynamic random access memory.

9. The processor of claim 5 wherein the plurality of processing units are essentially identical units each having a plurality of sides, each side having a plurality of unidirectional data ports being an input port and an output port.

10. The processor of claim 9 wherein the input port is programmable to route incoming data to any one of the output ports.

11. The processor of claim 10 wherein each of the plurality of processing units has a plurality of control ports on each side including an input control port and an output control port, and wherein the input control port of a processing unit is programmable to route incoming command information to anyone of the output control ports of said processing unit.

12. The processor of claim 9 further comprising an interface to an external device, and wherein the output ports of one of said processing units are coupled to the input ports of an adjacent one of said processing units except that some of the output ports of an outlying one of said processing units are coupled to the external device interface.

13. The processor of claim 9 further comprising:

a second DMA unit, wherein there are at least four of said plurality of processing units, the data ports on a north side of first and second ones of said four processing units are coupled to the first DMA unit, the data ports on a south side of third and fourth ones of said four processing units are coupled to the second DMA unit, and the data ports of a south side of the first and second processing units are coupled to the data ports of a north side of the third and fourth processing units.

14. The processor of claim 13 further comprising an interface to an external device, wherein some of the data ports of east and west sides of the processing units are coupled to the external device interface.

15. The processor of claim 5 further comprising a central processing unit to read and execute instructions that configure the data ports and the DMA unit to create a data channel from one of the processing units to external memory.

16. The processor of claim 5 further comprising a host interface unit to receive instructions, from an external host controller, that configure the data ports and the DMA unit to create a data path from one of the processing units to external memory.

17. A system comprising:

a host controller;

external memory;

a data driven processor having a memory access unit to interface the external memory, a plurality of processing units each having a plurality of data ports, the data ports being coupled to each other and programmable to allow data flow from any one of the processing units to another and from any one of the processing units to the memory access unit, and a host interface unit to receive instructions from the external host controller that configure the data ports and the memory unit to create a data path from one of the processing units through a data channel to the external memory, wherein one of the processing units has a control port which it uses to write data location information to the memory access unit; and

one of a rechargeable battery and a fuel cell coupled to power the external memory, the host controller, and the data driven processor.

18. The system of claim 17 wherein the host controller includes an embedded processor and its associated main memory.

19. The system of claim 17 wherein the coupling of each pair of data ports from adjacent processing units is a point-to-point, unidirectional connection.

20. The system of claim 19 wherein each of the processing units has a core programming element (PE) that can be programmed to execute instructions that operate on incoming data received via an input data port of that processing unit, an input PE that can read data from any one of a plurality of input data ports of that processing unit, and an output PE that can write data to any one of a plurality of output data ports of that processing unit.

21. The system of claim 20 wherein the core PE of each processing unit can execute its instructions independently of a data path that is operating through a pair of said input and output data ports of that processing unit.

22. The system of claim 17 wherein the data location information that is sent through the control port includes information about the size and display location of a block of image data.

24. The system of claim 17 wherein each of the processing units has a plurality of control ports that are connected to each other in a mesh arrangement so that the data channel information, including one of a read and write command, address, and memory access unit channel identifier, can originate from any one of the processing units and be routed to the memory access unit via a logical control channel programmed in the mesh arrangement.

23. A system comprising:

external memory;

a data driven processor having a memory access unit to interface the external memory, a plurality of processing units each having a plurality of data ports, the data ports being coupled to each other and programmable to allow data flow from any one of the processing units to another and from any one of the processing units to the memory access unit, and a central processing unit to receive and execute instructions that configure the data ports and the memory unit to create a data path from one of the processing units through a data channel to the external memory, wherein one of the processing units has a control port which it uses to write data channel information to the memory access unit; and

one of a rechargeable battery and a fuel cell coupled to power the external memory and the data driven processor.

25. The system of claim 23 wherein the coupling of each pair of data ports from adjacent processing units is a point-to-point, unidirectional connection.

26. The system of claim 23 wherein each of the processing units has a plurality of control ports that are coupled to each other and are programmable to allow data channel information to be sent from any one of the processing units to the memory access unit.

27. A data processor comprising:

means for translating higher level read and write commands into lower level memory access commands;

a plurality of means for consuming data;

means for implementing programmable data paths to supply data to and accept data from any one of said plurality of data consumption means;

means for receiving instructions, from other than said plurality of data consumption means, to configure the programmable data path implementation means, the plurality of data consumption means, and the higher level read and write translation means; and

means for implementing a programmable control path to transfer higher level read and write commands from one of said plurality of data consumption means to the higher level read and write translation means.

28. The processor of claim 27 further comprising means for ensuring that said lower level memory accesses meet signal level and timing requirements of external memory.

29. The processor of claim 27 further comprising means for expanding the data processor.