Lowered PU power usage method and apparatus
First Claim
1. A method of conserving power in a multiprocessor device including a plurality of PUs (processor units), comprising the steps of:
- providing a plurality of blocking channels associated with a like plurality of PUs;
setting a PU to a sleep mode when the channel is blocked for the operation the processor is attempting; and
returning a PU to normal power conditions when a given type of channel event occurs.
1 Assignment
0 Petitions
Accused Products
Abstract
Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.
-
Citations
19 Claims
-
1. A method of conserving power in a multiprocessor device including a plurality of PUs (processor units), comprising the steps of:
-
providing a plurality of blocking channels associated with a like plurality of PUs;
setting a PU to a sleep mode when the channel is blocked for the operation the processor is attempting; and
returning a PU to normal power conditions when a given type of channel event occurs.
-
-
2. A method of conserving the use of electrical energy in a computer processor, comprising:
-
providing a mechanism for blocking transactions; and
placing the processor into a low-power state when a blocked transaction exists. - View Dependent Claims (3, 4, 5, 6, 7)
-
-
8. A method of conserving the use of electrical energy in a multiprocessor system, comprising:
-
providing a mechanism for blocking transactions in at least a plurality of processors of the multiprocessor system; and
placing the a processor into a low-power state when a blocked transaction exists. - View Dependent Claims (9, 10, 11)
-
-
12. Apparatus for conserving the use of electrical energy in a processor, comprising:
-
blocking channel data storage means operable to contain data for use in connection with the environment outside the processor; and
low power means operable to place the processor in a low power mode while awaiting a response from the environment.
-
-
13. Apparatus for conserving the use of electrical energy in a processor, comprising:
-
blocking channel data storage means operable to contain data for use in connection with the environment outside the processor; and
low power means operable to place the processor in a low power mode when the blocking channel is at least one of full and empty.
-
-
14. Apparatus for conserving the use of electrical energy in a processor, comprising:
-
blocking channel data storage means operable to contain data for use in connection with the environment outside the processor; and
low power means operable to place the processor in a low power mode while awaiting a response from the environment.
-
-
15. Apparatus for conserving the use of electrical energy in a processor, comprising:
-
blocking transaction means;
monitoring means operable to place the processor in a low-power state when a blocked transaction condition is detected.
-
-
16. A method of conserving the use of electrical energy in a computer processor, comprising:
-
normally keeping the processor in a low power state; and
awakening the processor to an active state for only as long as the processor can usefully process data. - View Dependent Claims (17)
-
-
18. Apparatus for conserving the use of electrical energy in a computer processor, comprising:
-
a processor normally maintained in a low power state; and
detection means operable to awaken the processor to an active state for only as long as the detection means ascertains that the processor can usefully process data. - View Dependent Claims (19)
-
Specification