High data rate differential signal line design for uniform characteristic impedance for high performance integrated circuit packages

• US 20040268271A1
• Filed: 06/25/2003
• Published: 12/30/2004
• Est. Priority Date: 06/25/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Agrawal, Amit P.
• Granted Patent: US 7,013,437 B2
• Time in Patent Office: Days
• US Class Current: 333/12
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1903 including wave guides
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01P 5/02 with invariable factor of coupling H01P5/12 takes precedence choke joints H01P1/04, H01P1/06
• CPC Class Codes: H05K 1/025 Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H01L23/66
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09236 Parallel layout
• CPC Class Codes: H05K 2201/09727 Varying width along a single conductor; Conductors or pads having different widths
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array

Abstract

Provided is an apparatus that includes an integrated circuit (IC) mounted on a chip carrier. The IC has one or more differential pair circuits coupled thereto and the chip carrier has a signal escaping portion and a remaining portion. The apparatus also includes differential signal lines coupled to the differential pair circuits, the differential signal lines (i) extending through the chip carrier and (ii) having first and second segments. The first segment extends through the escaping portion and the second segment extends through the remaining portion. The first and second segments have respective first and second widths.

Claims

1. An apparatus comprising:

an integrated circuit (IC) mounted on a chip carrier, the IC having one or more differential pair circuits coupled thereto, the chip carrier having a signal escaping portion and a remaining portion; and

differential signal lines coupled to the differential pair circuits, the differential signal lines (i) extending through the chip carrier and (ii) having first and second segments;

wherein the first segment extends through the escaping portion and the second segment extends through the remaining portion; and

wherein the first and second segments have respective first and second widths.

2. The apparatus of claim 1, wherein the escaping portion is configured for escaping transmitted signals from the IC.

3. The apparatus of claim 1, wherein the first and second widths provide substantially uniform impedance characteristics across the signal lines.

4. The apparatus of claim 3, wherein the impedance is within a range of about 90 to 110 ohms.

5. The apparatus of claim 1, wherein the second width is larger than the first width.

6. The apparatus of claim 1, wherein the differential signal lines include respective inverting and non-inverting paths;

and

wherein the paths along the escaping portion are separated by a first spacing and the paths along the remaining portion are separated by at least a second spacing.

7. The apparatus of claim 6, wherein the second spacing is larger that the first spacing.

8. The apparatus of claim 6, wherein the first and second spacings cooperate to reduce cross-talk between the inverting and non-inverting paths.

9. The apparatus of claim 6, wherein the first and second widths and the first and second spacings are determined based upon modeling and simulations.

10. The apparatus of claim 1, wherein the signal lines are configured to transmit high data rate signals.

11. The apparatus of claim 10, wherein a data rate of the high data rate signals is greater than or equal to about 5 gigabits per second.

12. The apparatus of claim 6, wherein the inverting and non-inverting paths are adjacent to one another.

13. An integrated circuit (IC) (i) having a differential circuit coupled thereto and (ii) mounted on a chip carrier, the differential circuit including a signal escaping portion and a remaining portion, the IC comprising:

differential signal lines extending through the chip carrier and including first and second segments;

wherein the first segment extends through the signal escaping portion and the second segment extends through the remaining portion;

wherein the first and second segments have respective first and second widths; and

wherein the first and second widths provide substantially uniform impedance characteristics across the signal lines.

14. The IC of claim 13, wherein the first and second widths provide substantially uniform impedance characteristics across the signal lines.

15. The IC of claim 13, wherein the second width is larger than the first width.

16. The IC of claim 13, wherein the differential signal lines include respective inverting and non-inverting paths;

and

wherein the paths along the escaping portion are separated by a first spacing and the paths along the remaining portion are separated by at least a second spacing.

17. The IC of claim 16, wherein the second spacing is larger that the first spacing.

18. The IC of claim 17, wherein the first and second spacings cooperate to reduce cross-talk between the inverting and non-inverting paths.

19. The IC of claim 18, wherein the first and second widths and the first and second spacings are determined based upon modeling and simulations.

20. The IC of claim 13, wherein the signal lines are configured to transmit signals having a data-rate greater than about 5 gigabits per second.