High-performance one-transistor memory cell
First Claim
1. A memory cell, comprising:
- an access transistor having a floating node, the floating node to store a charge indicative of a memory state of the memory cell; and
a diode exhibiting Negative Differential Resistance (NDR) behavior connected between the floating node and a diode reference potential line, the diode including an anode, a cathode and an intrinsic region between the anode and the cathode, the intrinsic region of the diode to assist with stabilizing the memory state of the memory cell.
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Accused Products
Abstract
One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes. Other aspects and embodiments are provided herein.
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Citations
100 Claims
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1. A memory cell, comprising:
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an access transistor having a floating node, the floating node to store a charge indicative of a memory state of the memory cell; and
a diode exhibiting Negative Differential Resistance (NDR) behavior connected between the floating node and a diode reference potential line, the diode including an anode, a cathode and an intrinsic region between the anode and the cathode, the intrinsic region of the diode to assist with stabilizing the memory state of the memory cell. - View Dependent Claims (3, 4, 5)
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2. The memory cell of clam 1, wherein the cathode of the diode is connected to the floating node of the access transistor.
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6. A memory cell, comprising:
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an access transistor having a first diffusion region connected to a bit line, and a second diffusion region, the second diffusion region to store a charge indicative of a memory state of the memory cell;
a Negative Differential Resistance (NDR) diode connected between the second diffusion region and a diode reference potential line, the diode including;
an anode;
a cathode;
an intrinsic region between the anode and cathode to assist with stabilizing the memory state of the memory cell; and
a diode gate operatively positioned with respect to the intrinsic region to enhance switching performance between memory states.
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7. A memory cell, comprising:
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an n-channel access transistor on a bulk semiconductor substrate, the n-channel access transistor having a first n-type diffusion region connected to a bit line and a second n-type diffusion region, the second n-type diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) n/i/p diode having an n-type anode connected to a diode reference potential line, a p-type cathode in contact with the second n-type diffusion region, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell.
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8. A memory cell, comprising:
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a p-channel access transistor on a bulk semiconductor substrate, the p-channel access transistor having a first p-type diffusion region connected to a bit line and a second p-type diffusion region, the second p-type diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) n/i/p diode having an n-type anode connected to a diode reference potential line, a p-type cathode formed with the second n-type diffusion region, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell.
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9. A memory cell, comprising:
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an n-channel access transistor on a bulk semiconductor substrate, the p-channel access transistor having a first n-type diffusion region connected to a bit line and a second n-type diffusion region, the second n-type diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) p/i/n diode having a p-type anode connected to a diode reference potential line, an n-type cathode formed with the second n-type diffusion region, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell.
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10. A memory cell, comprising:
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a p-channel access transistor on a bulk semiconductor substrate, the p-channel access transistor having a first p-type diffusion region connected to a bit line and a second p-type diffusion region, the second p-type diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) p/i/n diode having a p-type anode connected to a diode reference potential line, an n-type cathode in contact with the second p-type diffusion region, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell.
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11. A memory cell, comprising:
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an access transistor on a bulk semiconductor substrate, the access transistor having a first diffusion region connected to a bit line and a second diffusion region, the second diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) diode connected between the second diffusion region of the access transistor and a diode reference potential line, the diode having an anode, a cathode, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell, the diode being laterally oriented over the access transistor.
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12. A memory cell, comprising:
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an access transistor on a bulk semiconductor substrate, the access transistor having a first diffusion region connected to a bit line and a second diffusion region, the second diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) diode connected between the second diffusion region of the access transistor and a diode reference potential line, the diode having an anode, a cathode, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell, the diode being vertically oriented over the access transistor.
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13. A memory cell, comprising:
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an n-channel access transistor on a semiconductor-on-insulator substrate, the n-channel access transistor having a floating body and a first n-type diffusion region connected to a bit line and a second n-type diffusion region, the second n-type diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) n/i/p diode having an n-type anode connected to a diode reference potential line, a p-type cathode in contact with the second n-type diffusion region, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell, wherein intentionally-generated charges in the floating body of the access transistor enhance diode switching.
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14. A memory cell, comprising:
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a p-channel access transistor on a semiconductor-on-insulator substrate, the p-channel access transistor having a floating body and a first p-type diffusion region connected to a bit line and a second p-type diffusion region, the second p-type diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) n/i/p diode having an n-type anode connected to a diode reference potential line, a p-type cathode formed with the second n-type diffusion region, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell, wherein intentionally-generated charges in the floating body of the access transistor enhance diode switching.
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15. A memory cell, comprising:
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an n-channel access transistor on a semiconductor-on-insulator substrate, the p-channel access transistor having a floating body and a first n-type diffusion region connected to a bit line and a second n-type diffusion region, the second n-type diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) p/i/n diode having a p-type anode connected to a diode reference potential line, an n-type cathode formed with the second n-type diffusion region, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell, wherein intentionally-generated charges in the floating body of the access transistor enhance diode switching.
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16. A memory cell, comprising:
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a p-channel access transistor on a semiconductor-on-insulator substrate, the p-channel access transistor having a floating body and a first p-type diffusion region connected to a bit line and a second p-type diffusion region, the second p-type diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) p/i/n diode having a p-type anode connected to a diode reference potential line, an n-type cathode in contact with the second p-type diffusion region, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell, wherein intentionally-generated charges in the floating body of the access transistor enhance diode switching.
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17. A memory cell, comprising:
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an access transistor on a semiconductor-on-insulator substrate, the access transistor having a floating body and a first diffusion region connected to a bit line and a second diffusion region, the second diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) diode connected between the second diffusion region of the access transistor and a diode reference potential line, the diode having an anode, a cathode, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell, the diode being laterally oriented in the floating body of the access transistor, wherein intentionally-generated charges in the floating body of the access transistor enhance diode switching.
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18. A memory cell, comprising:
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an access transistor on a semiconductor-on-insulator substrate, the access transistor having a floating body and a first diffusion region connected to a bit line and a second diffusion region, the second diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) diode connected between the second diffusion region of the access transistor and a diode reference potential line, the diode having an anode, a cathode, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell, the diode being laterally oriented over the access transistor, wherein intentionally-generated charges in the floating body of the access transistor enhance diode switching.
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19. A memory cell, comprising:
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an access transistor on a semiconductor-on-insulator substrate, the access transistor having a floating body and a first diffusion region connected to a bit line and a second diffusion region, the second diffusion region to store a charge indicative of a memory state of the memory cell; and
a Negative Differential Resistance (NDR) diode connected between the second diffusion region of the access transistor and a diode reference potential line, the diode having an anode, a cathode, and an intrinsic region between the anode and the cathode to assist with stabilizing the memory state of the memory cell, the diode being vertically oriented over the access transistor, wherein intentionally-generated charges in the floating body of the access transistor enhance diode switching.
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20. A memory cell, comprising:
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an access transistor, including;
a body region;
a first diffusion region electrically connected to a bit line;
a second diffusion region separated from the first diffusion region by a channel area in the body region;
a gate separated from the channel area by a gate insulator, the gate electrically connected to a word line;
a Negative Differential Resistance (NDR) diode, including an anode, a cathode, and an intrinsic region between the anode and the cathode, the diode being connected between the second diffusion region and a diode reference potential line, wherein the memory cell is operative to store and sense a charge in the second diffusion region that is representative of a memory state. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A memory cell, comprising:
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an access transistor formed in a bulk semiconductor structure, the access transistor including a first diffusion region separated from a second diffusion region by a channel region, and further including a gate separated from the channel region by a gate insulator, wherein the first diffusion region is connected to a bit line and the gate is connected to a first word line; and
a gate-controlled Negative Differential Resistance (NDR) diode connected between a reference potential line and the second diffusion region, the diode including an anode, a cathode, an intrinsic region positioned between the anode and the cathode, and a diode gate operably positioned with respect to the intrinsic region, the diode gate being connected to a second word line. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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42. A memory cell, comprising:
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an semiconductor-on-insulator (SOI) structure, including an SOI access transistor including a first diffusion region separated from a second diffusion region by a channel region, and further including a gate separated from the channel region by a gate insulator, wherein the first diffusion region is connected to a bit line and the gate is connected to a first word line; and
a Negative Differential Resistance (NDR) diode connected between the second diffusion region and a reference potential line, the diode including an anode, a cathode, and an intrinsic region between the anode and the cathode. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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54. A memory cell, comprising:
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an access transistor, the access transistor including a first diffusion region separated from a second diffusion region by a channel region, and further including a gate separated from the channel region by a gate insulator, wherein the first diffusion region is connected to a bit line and the gate is connected to a first word line; and
a Negative Differential Resistance (NDR) p/i/n diode connected between a diode reference potential line and the second diffusion region, the p/i/n diode including a p-type anode, an n-type cathode, and an intrinsic region positioned between the anode and the cathode. - View Dependent Claims (55, 56, 57, 58, 59, 60, 61, 62)
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63. A memory cell, comprising:
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an access transistor, including a first diffusion region separated from a second diffusion region by a channel region, and further including a gate separated from the channel region by a gate insulator, wherein the first diffusion region is connected to a bit line and the gate is connected to a first word line; and
a Negative Differential Resistance (NDR) n/i/p diode connected between a diode reference potential line and the second diffusion region, the n/i/p including an n-type anode, a p-type cathode, and an intrinsic region positioned between the anode and the cathode. - View Dependent Claims (64, 65, 66, 67, 68, 69, 70, 71)
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72. A memory device, comprising:
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a memory array, including a plurality of memory cells in rows and columns;
a number of word lines, each word line connected to a row of memory cells;
a number of bit lines, each bit line connected to a column of memory cells;
at least one reference line to provide a reference potential to the memory cells;
control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations, wherein each memory cell includes;
an access transistor, including a body region, a first diffusion region electrically connected to one of the bit lines, a second diffusion region separated from the first diffusion region by a channel area in the body region, and a gate separated from the channel area by a gate insulator and electrically connected to one of the word lines; and
a Negative Differential Resistance (NDR) diode, including an anode, a cathode, and an intrinsic region between the anode and the cathode, the diode being connected between the second diffusion region and a diode reference line, wherein the memory cell is adapted to store a charge in the second diffusion region of the access transistor to indicate a stable memory state. - View Dependent Claims (73, 74, 75, 76, 77, 78, 79)
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80. A method for operating a memory cell, comprising:
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selectively switching a diode with an intrinsic region between a conducting “
on”
state and a non-conducting “
off”
state to represent a binary memory state, wherein the intrinsic region is between a cathode and an anode of the diode; and
sensing the binary memory state, including connecting a bit line to the diode and detecting a bit line potential change based on current flowing through the diode. - View Dependent Claims (81, 82, 83)
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84. A method for operating a memory cell, comprising:
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performing a write-one operation, including actuating an access transistor to electrically connect a bit line to a floating node of the access transistor, and forward biasing a diode connected to the floating node of an access transistor such that a charge is stored on the floating node to hold the diode in a conducting “
on”
state;
performing a read-one operation, including actuating the access transistor to electrically connect the bit line to the floating node, and sensing a significant change in a bit line potential attributed to current flowing through the diode and the access transistor;
performing a write-zero operation, including actuating the access transistor to electrically connect the bit line to the floating node, reverse biasing the diode and holding the diode in a non-conducting “
off”
state; and
performing a read-zero operation, including actuating the access transistor to electrically connect the bit line to the floating node, and sensing that there is not a significant change to the bit line potential.
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85. A method for forming a memory cell, comprising:
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forming an access transistor with a floating node, the floating node to store a charge indicative of a memory state of the memory cell; and
forming a Negative Differential Resistance (NDR) diode connected between the floating node and a reference potential line, wherein forming a diode includes forming a diode with an intrinsic region between a cathode and an anode of the diode, the intrinsic region having a desired geometry to assist with stabilizing the memory state of the memory cell. - View Dependent Claims (86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100)
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Specification