Semiconductor storage device, display device and portable electronic equipment

• US 20050001243A1
• Filed: 05/19/2004
• Published: 01/06/2005
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Iwata, Hiroshi, Shibata, Akihide, Yaoi, Yoshifumi, Morikawa, Yoshinao, Nawaki, Masaru
• Granted Patent: US 7,009,884 B2
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements are arranged and a program verify circuit 30. The memory element 1, 33 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on opposite sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies 109 that are located on opposite sides of the gate electrode 104 and have a function of retaining electric charge. A program load register 32 of the program verify circuit 30 eliminates a state that a memory element 33 which has initially been verified as having been correctly programmed needs to be further programmed.

Claims

1. A semiconductor storage device comprising a memory cell array having a plurality of memory elements, and a program verify circuit for controlling application of programming voltages into the plurality of memory elements, wherein

each of the memory elements comprises:

a gate electrode formed on a semiconductor layer via a gate insulator;

a channel region arranged below the gate electrode via the gate insulator;

diffusion regions which are arranged on opposite sides of the channel region and which have a conductive type opposite to that of the channel region; and

memory function bodies which are formed on opposite sides of the gate electrode and which have a function of retaining electric charge or polarization, and wherein

the program verify circuit comprises;

a comparator for comparing a current state of each memory element being programmed with a state to which the memory element is to be programmed; and

a program load circuit which is connected to the comparator and which stores, for each memory element, a value outputted from the comparator and indicating whether or not the memory element should be further programmed,

the program load circuit including a circuit for, once the memory element has initially been verified by the comparator as having been programmed, precluding storing for each memory element a value indicating that the memory element needs to be further programmed.

2. The semiconductor storage device as claimed in claim 1, wherein the circuit for precluding storing for each memory element the value comprises a latch and a feedback circuit for controlling an input to the latch depending on a state of the latch when a value outputted from the comparator is applied.

3. The semiconductor storage device as claimed in claim 1, further comprising a flag circuit for prohibiting overprogramming of the memory element.

4. The semiconductor storage device as claimed in claim 3, wherein the flag circuit comprises a register for receiving an input from the program load circuit indicating whether the memory element is programmed or to be programmed.

5. The semiconductor storage device as claimed in claim 3, further comprising a controller circuit for resetting the program load circuit and the flag circuit.

11. The semiconductor storage device as claimed in claim 1, wherein at least part of each of the memory function bodies of the memory element are overlapped with part of each of the diffusion regions.

12. The semiconductor storage device as claimed in claim 1, wherein each of the memory function bodies of the memory element includes a film having a surface roughly parallel to a surface of the gate insulator and having a function of retaining electric charge.

13. The semiconductor storage device as claimed in claim 1, wherein each of the memory function bodies of the memory element further includes a charge retention film extending roughly parallel to a side face of the gate electrode.

14. The semiconductor storage device as claimed in claim 1, wherein the semiconductor layer of the memory element has a region located between the diffusion region and the channel region and doped more heavily than vicinities of a semiconductor layer surface below the gate electrode.

15. The semiconductor storage device as claimed in claim 1, wherein the memory element has an insulation film which insulates a film having a surface roughly parallel to a surface of the gate insulator and a function of retaining electric charge from the channel region or the semiconductor layer, and the insulation film has a film thickness thinner than a film thickness of the gate insulator and is not smaller than 0.8 nm.

16. Portable electronic equipment comprising the semiconductor storage device claimed in claim 1.

6. A semiconductor storage device comprising a memory cell array having a plurality of memory elements, and a program verify circuit for controlling application of programming voltages into the plurality of memory elements, wherein

each of the memory elements comprises:

a gate electrode formed on a semiconductor layer via a gate insulator;

a channel region arranged below the gate electrode via the gate insulator;

diffusion regions which are arranged on opposite sides of the channel region and which have a conductive type opposite to that of the channel region; and

memory function bodies which are formed on opposite sides of the gate electrode and which have a function of retaining electric charge or polarization, and wherein

the program verify circuit comprises;

comparator means for comparing a current state of each memory element being programmed with a state to which the memory element is to be programmed; and

storage means which is connected to the comparator means and which stores, for each memory element, a value outputted from the comparator means and indicating whether or not the memory element should be further programmed,

the storage means including means for, once the memory element has initially been verified by the comparator as having been programmed, precluding storing for each memory element a value indicating that the memory element needs to be further programmed.

7. The semiconductor storage device as claimed in claim 6, wherein the means for precluding storing for each memory element the value comprises a latch and a feedback circuit for controlling an input to the latch depending on a state of the latch when a value outputted from the comparator means is applied.

8. The semiconductor storage device as claimed in claim 6, further comprising means for prohibiting overprogramming of the memory element.

9. The semiconductor storage device as claimed in claim 8, wherein the means for prohibiting overprogramming of the memory element comprises a register for receiving an input from the storage means indicating whether the memory element is programmed or to be programmed.

10. The semiconductor storage device as claimed in claim 8, further comprising a controller circuit for resetting the storage means and the means for prohibiting overprogramming of the memory element.

17. The semiconductor storage device as claimed in claim 6, wherein at least part of each of the memory function bodies of the memory element are overlapped with part of each of the diffusion regions.

18. The semiconductor storage device as claimed in claim 6, wherein each of the memory function bodies of the memory element includes a film having a surface roughly parallel to a surface of the gate insulator and having a function of retaining electric charge.

19. The semiconductor storage device as claimed in claim 6, wherein each of the memory function bodies of the memory element further includes a charge retention film extending roughly parallel to a side face of the gate electrode.

20. The semiconductor storage device as claimed in claim 6, wherein the semiconductor layer of the memory element has a region located between the diffusion region and the channel region and doped more heavily than vicinities of a semiconductor layer surface below the gate electrode.

21. The semiconductor storage device as claimed in claim 6, wherein the memory element has an insulation film which insulates a film having a surface roughly parallel to a surface of the gate insulator and a function of retaining electric charge from the channel region or the semiconductor layer, and the insulation film has a film thickness thinner than a film thickness of the gate insulator and is not smaller than 0.8 nm.

22. Portable electronic equipment comprising the semiconductor storage device claimed in claim 6.