Semiconductor device having verical MOS gate structure and method of manufacturing the same

• US 20050001264A1
• Filed: 04/22/2004
• Published: 01/06/2005
• Est. Priority Date: 04/23/2003
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawaguchi, Yusuke, Nakagawa, Akio, Ono, Syotaro
• Granted Patent: US 7,227,225 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.

Claims

1. A semiconductor device comprising:

a first semiconductor region of a first conductivity type;

a second semiconductor region of a second conductivity type formed on the first semiconductor region;

a third semiconductor region of the first conductivity type formed on a part of the second semiconductor region;

a trench formed to range from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region, the trench penetrating the third semiconductor region, a depth of the trench being shorter than a depth of a deepest bottom portion of the second semiconductor region, and the trench having no second semiconductor region under its bottom surface;

a gate insulating film formed on both facing side surfaces of the trench;

first and second gate electrodes formed on the gate insulating film on the respective facing side surfaces of the trench, the first and second electrodes being separated from each other; and

a first conductive material formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened between the conductive material and the first and second gate electrodes.

2. A semiconductor device according to claim 1, further comprising a fourth semiconductor region of the first conductivity type formed between the bottom surface of the trench and the first semiconductor region, the fourth semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region.

3. A semiconductor device according to claim 2, the fourth semiconductor region being arranged apart in boundary regions of the first semiconductor region and the second semiconductor region.

4. A semiconductor device according to claim 1, further comprising:

a fifth semiconductor region of the second conductivity type formed on a part of the second semiconductor region, the fifth semiconductor region having an impurity concentration higher than an impurity concentration of the second semiconductor region; and

a source electrode formed on the fifth semiconductor region and the third semiconductor region.

5. A semiconductor device according to claim 4, the first conductive material being electrically connected to the source electrode.

6. A semiconductor device according to claim 1, the first conductive material being a floating electrode.

7. A semiconductor device according to claim 1, the separated first and second gate electrodes being connected to each other at a part thereof inside the trench.

8. A semiconductor device according to claim 7, further comprising a sixth semiconductor region of the second conductivity type formed between the first semiconductor region and a bottom surface of the trench located under the part, at which the separated first and second gate electrode are connected, the sixth semiconductor region having an impurity concentration higher than an impurity concentration of the second semiconductor region.

9. A semiconductor device according to claim 1, further comprising an insulating film formed between the bottom surface of the trench and the separated first and second gate electrodes, and between the bottom surface of the trench and the first conductive material, and insulating film having a film thickness greater than a thickness of the gate insulating film formed on the side surfaces of the trench.

10. A semiconductor device according to claim 1, the first semiconductor region forming a drain region, the second semiconductor region forming a base region, and the third semiconductor region forming a source region, and the first to third semiconductor regions being formed into a MOS field-effect transistor.

11. A semiconductor device according to claim 1, further comprising a second conductive material formed under the first conductive material and extending below the first and the second gate electrodes.

12. A semiconductor device comprising:

a first semiconductor region of a first conductivity type;

a second semiconductor region of a second conductivity type formed on the first semiconductor region;

a third semiconductor region of the first conductivity type formed on the second semiconductor region;

a trench penetrating the third semiconductor region and the second semiconductor region from a surface of the third semiconductor region, a depth of the trench being shorter than a depth of a deepest bottom portion of the second semiconductor region;

a gate insulating film formed on both facing side surfaces of the trench;

a gate electrode formed on the gate insulating film in the trench; and

an insulating film formed between a bottom surface of the trench and the gate electrode, the insulating film having a film thickness greater than a thickness of the gate insulating film formed on the side surfaces of the trench.

13. A semiconductor device according to claim 12, further comprising a fourth semiconductor region of the first conductivity type formed between the bottom surface of the trench and the first semiconductor region, the fourth semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region.

14. A semiconductor device according to claim 13, the fourth semiconductor region, formed between the bottom surface of the trench and the first semiconductor region, being arranged apart in boundary regions of the first semiconductor region and the second semiconductor region.

15. A semiconductor device according to claim 12, further comprising:

a fifth semiconductor region of the second conductivity type formed on a part of the second semiconductor region, the fifth semiconductor region having an impurity concentration higher than an impurity concentration of the second semiconductor region; and

a source electrode formed on the fifth semiconductor region and the third semiconductor region.

16. A semiconductor device according to claim 15, the conductive material being electrically connected to the source electrode.

17. A semiconductor device according to claim 12, the first semiconductor region forming a drain region, the second semiconductor region forming a base region, and the third semiconductor region forming a source region, and the first to third semiconductor regions being formed into a MOS field-effect transistor.

18. A method of manufacturing a semiconductor device, comprising:

forming a first semiconductor region on a semiconductor substrate;

forming a trench of a predetermined depth in the first semiconductor region;

forming a second semiconductor region on a surface region of the first semiconductor region, the second semiconductor region contacting side surfaces of the trench;

forming a gate insulating film on the facing side surfaces of the trench;

depositing a conductive film on the gate insulating film;

subjecting the conductive film to anisotropic etching, and leaving the conductive film only on the side surfaces of the trench; and

ion-implanting impurities into the first semiconductor region by self alignment, with the conductive film on the side surfaces of the trench used as a mask, and forming a fourth semiconductor region under a bottom surface of the trench.