Power semiconductor devices having linear transfer characteristics when regions therein are in velocity saturation modes and methods of forming and operating same

• US 20050001268A1
• Filed: 05/28/2004
• Published: 01/06/2005
• Est. Priority Date: 06/23/2000
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Baliga, Bantval Jayant
• Application Number:
  US10/856,417
• Publication Number:
  US 20050001268A1
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Power MOSFET devices provide highly linear transfer characteristics (e.g., I_d v. V_g) and can be used effectively in linear power amplifiers. These linear transfer characteristics are provided by a device having a channel that operates in a linear mode and a drift region that simultaneously supports large voltages and operates in a current saturation mode. A relatively highly doped transition region is provided between the channel region and the drift region. Upon depletion, this transition region provides a potential barrier that supports simultaneous linear and current saturation modes of operation. Highly doped shielding regions may also be provided that contribute to depletion of the transition region.

Claims

1. An integrated power device, comprising:

an insulated-gate field effect transistor that is configured to support an inversion-layer channel during forward on-state conduction, said inversion-layer channel being operable in a linear mode of operation while a drain region of said insulated-gate field effect transistor simultaneously operates in a velocity saturation mode of operation.

2. The device of claim 1, wherein said transistor comprises:

a semiconductor substrate having a source region and drain contact region of first conductivity type therein;

a base region of second conductivity type extending adjacent a surface of said semiconductor substrate;

a transition region of first conductivity type that extends to the surface and forms a rectifying junction with said base region;

an insulated gate electrode extending on the surface and opposite said source, base and transition regions so that application of a gate bias of sufficient magnitude thereto induces formation of the inversion-layer channel between said source region and said transition region; and

a drift region of first conductivity type that extends between said transition region and said drain contact region, forms a first non-rectifying junction with said transition region and has a first conductivity type doping concentration therein on the drift region side of the first non-rectifying junction that is less than a first conductivity type doping concentration on the transition region side of the first non-rectifying junction.

3. The device of claim 2, further comprising:

means, adjacent said transition region, for fully depleting said transition region while the inversion-layer channel is operating in the linear mode.

4. The device of claim 3, wherein said means for fully depleting said transition region comprises a buried region of second conductivity type disposed adjacent said transition region.

5. The device of claim 4, wherein said buried region forms a non-rectifying junction with said base region.

6. The device of claim 3, wherein said means for fully depleting said transition region comprises a region of second conductivity type that is contiguous with said base region.

7. The device of claim 3, further comprising:

a trench that extends in said semiconductor substrate and has a sidewall that defines an interface with said transition region; and

an insulated source electrode that extends in said trench and is electrically connected to said source region.

8. The device of claim 7, wherein the device is a vertical device;

wherein the transistor is a lateral transistor;

wherein said semiconductor substrate has first and second opposing faces;

wherein said insulated gate electrode and said source region are formed adjacent the first face; and

wherein said drain contact region is formed adjacent the second face.

9. The device of claim 8, wherein the surface and the first face are coextensive.

10. The device of claim 9, wherein said drift region extends along the sidewall of said trench.

11. The device of claim 3, wherein said means for filly depleting said transition region comprises:

a first control region of second conductivity type that forms a rectifying junction with said transition region and forms a non-rectifying junction with said base region; and

a second control region of second conductivity type that extends in said transition region and forms a rectifying junction therewith.

12. The device of claim 11, further comprising a source contact that extends on said source region and is electrically connected to said second control region.

13. The device of claim 12, wherein said source contact extends on said base region;

and wherein said first control region is electrically coupled to said source contact by said base region.

14. The device of claim 5, further comprising a source contact that extends on said source region;

and wherein said source contact extends opposite said transition region and forms a MIS junction therewith.

15. A UMOSFET, comprising:

a semiconductor substrate having a source region and a drain contact region of first conductivity type therein;

a trench in said substrate;

an insulated gate electrode in said trench;

a base region of second conductivity type in said semiconductor substrate, said base region extending to a sidewall of said trench so that application of a gate bias of sufficient magnitude to said insulated gate electrode induces formation of an inversion-layer channel in said base region;

a drift region of first conductivity type on the drain contact region, said drift region extending to the sidewall of said trench; and

a transition region that extends between said drift region and said base region and forms non-rectifying and rectifying junctions therewith, respectively, said transition region having a higher first conductivity type doping concentration therein relative to a first conductivity type doping concentration in a portion of said drift region extending adjacent the non-rectifying junction.

16-111. -111. (Cancelled)