Thin film memory, array, and operation method and manufacture method therefor
First Claim
1. A thin film memory cell comprising:
- a semiconductor thin film having a first principal surface and a second principal surface that faces the first principal surface;
a first gate insulating film formed on the first principal surface of the semiconductor thin film;
a first conductive gate formed on the first gate insulating film;
a first semiconductor region and a second semiconductor region which are spaced apart from each other across the first conductive gate, which are insulated from the first conductive gate, which are in contact with the semiconductor thin film, and which have a first conductivity type; and
a third semiconductor region which has an opposite conductivity type opposite to the first conductivity type and which is in contact with the semiconductor thin film. wherein a portion of the semiconductor thin film that is sandwiched between the first semiconductor region and the second semiconductor region forms a first channel formation semiconductor thin film portion, wherein the semiconductor thin film is extended between the first channel formation semiconductor thin film portion and the third semiconductor region of the opposite conductivity type to form a second channel formation semiconductor thin film portion, and wherein a second gate insulating film is formed on the extended portion of the semiconductor thin film and a second conductive gate is formed on the second gate insulating film.
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Accused Products
Abstract
A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.
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Citations
61 Claims
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1. A thin film memory cell comprising:
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a semiconductor thin film having a first principal surface and a second principal surface that faces the first principal surface;
a first gate insulating film formed on the first principal surface of the semiconductor thin film;
a first conductive gate formed on the first gate insulating film;
a first semiconductor region and a second semiconductor region which are spaced apart from each other across the first conductive gate, which are insulated from the first conductive gate, which are in contact with the semiconductor thin film, and which have a first conductivity type; and
a third semiconductor region which has an opposite conductivity type opposite to the first conductivity type and which is in contact with the semiconductor thin film. wherein a portion of the semiconductor thin film that is sandwiched between the first semiconductor region and the second semiconductor region forms a first channel formation semiconductor thin film portion, wherein the semiconductor thin film is extended between the first channel formation semiconductor thin film portion and the third semiconductor region of the opposite conductivity type to form a second channel formation semiconductor thin film portion, and wherein a second gate insulating film is formed on the extended portion of the semiconductor thin film and a second conductive gate is formed on the second gate insulating film. - View Dependent Claims (2, 3, 4, 5, 9, 10, 11, 12, 13, 15, 17, 22, 24, 25, 27, 28, 29, 31, 32, 37, 38, 39, 40, 42, 44, 45, 46, 48, 50, 55, 56, 57, 59, 60)
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6. A thin film memory cell comprising:
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a semiconductor thin film having a first principal surface and a second principal surface that faces the first principal surface;
a first gate insulating film formed on the first principal surface of the semiconductor thin film;
a first conductive gate formed on the first gate insulating film;
a first semiconductor region and a second semiconductor region which are spaced apart from each other across the first conductive gate, which are insulated from the first conductive gate, which are in contact with the semiconductor thin film, and which have a first conductivity type; and
a third semiconductor region which has an opposite conductivity type opposite to the first conductivity type and which is in contact with the semiconductor thin film in a part of area below the first conductive gate, wherein a portion of the semiconductor thin film that is sandwiched between the first semiconductor region and the second semiconductor region forms a first channel formation semiconductor thin film portion, and wherein the semiconductor thin film is extended between the first channel formation semiconductor thin film portion and the third semiconductor region of the opposite conductivity type to form a second channel formation semiconductor thin film portion. - View Dependent Claims (7, 8, 14, 16, 18, 19, 20, 21, 23, 26, 30, 33, 34, 35, 36, 41, 43, 47, 49, 51, 52, 53, 54, 58, 61)
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Specification