Multi-test circuit interrupter locator and circuit interrupter tester

• US 20050001607A1
• Filed: 04/08/2004
• Published: 01/06/2005
• Est. Priority Date: 04/17/1998
• Status: Active Grant

• Current Assignee: Kerry Berland, Mitchell Budniak, Paul Berland, Ronald A. Coia, Thomas Mcgann
• Original Assignee: Kerry Berland, Mitchell Budniak, Paul Berland, Ronald A. Coia, Thomas Mcgann
• Inventors: Berland, Kerry, Berland, Paul, McGann, Thomas, Budniak, Mitchell, Coia, Ronald A.
• Granted Patent: US 7,471,075 B2
• Time in Patent Office: Days
• US Class Current: 324/67
• CPC Class Codes: G01R 31/3277 of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
• CPC Class Codes: G01R 31/67 Testing the correctness of wire connections in electric apparatus or circuits

Abstract

A testing system includes a hand-held transmitter that plugs into a receptacle electrically coupled to a selected branch circuit. The transmitter includes a circuit effective to test an arc fault circuit interrupter electrically coupled to the branch circuit by creating a first pulse on the branch circuit that is effective to trip the arc fault circuit interrupter. The transmitter can perform at least one additional test including: determining whether the receptacle is wired properly; determining a location of a circuit interrupting device electrically coupled to the branch circuit by creating a second pulse on the branch circuit that can be sensed by a receiver located proximately to the respective circuit interrupting device and broadly tuned about a frequency of the second pulse; and testing a ground fault circuit interrupter electrically coupled to the branch circuit by creating a third pulse on the branch circuit that is effective to trip the ground fault circuit interrupter.

Claims

1. A testing system comprising:

a hand-held transmitter that plugs into a receptacle electrically coupled to a selected branch circuit, the transmitter having a circuit effective to test an arc fault circuit interrupter electrically coupled to the selected branch circuit by creating a pulse on the branch circuit that is effective to trip the arc fault circuit interrupter,

wherein the transmitter can perform a test of determining whether the receptacle is wired properly.

2. The testing system of claim 1, wherein at least a portion of a circuit for performing the test of determining whether the receptacle is wired properly is common to the circuit effective to test the arc fault circuit interrupter.

3. The testing system of claim 1, wherein the hand-held transmitter is contained within a single enclosure.

4. A testing system comprising:

a hand-held transmitter that plugs into a receptacle electrically coupled to a selected branch circuit, the transmitter having a circuit effective to test an arc fault circuit interrupter electrically coupled to the selected branch circuit by creating a first pulse on the branch circuit that is effective to trip the arc fault circuit interrupter,

wherein the transmitter can perform a test of determining a location of a circuit interrupting device electrically coupled to the selected branch circuit by creating a second pulse on the branch circuit that can be sensed by a receiver located proximately to the respective circuit interrupting device and broadly tuned about a frequency of the second pulse.

5. The testing system of claim 4, wherein at least a portion of a circuit for performing the test of determining the location of the circuit interrupting device is common to the circuit effective to test the arc fault circuit interrupter.

6. The testing system of claim 4, wherein the first pulse has a higher current than the second pulse.

7. The testing system of claim 4, wherein the hand-held transmitter is contained within a single enclosure.

8. A testing system comprising:

a hand-held transmitter that plugs into a receptacle electrically coupled to a selected branch circuit, the transmitter having a circuit effective to test an arc fault circuit interrupter electrically coupled to the selected branch circuit by creating a first pulse on the branch circuit that is effective to trip the arc fault circuit interrupter,

wherein the transmitter can test a ground fault circuit interrupter electrically coupled to the selected branch circuit by creating a second pulse on the selected branch circuit that is effective to trip the ground fault circuit interrupter.

9. The testing system of claim 8, wherein at least a portion of a circuit for testing the ground fault circuit interrupter is common to the circuit effective to test the arc fault circuit interrupter.

10. The testing system of claim 8, wherein the first pulse has a higher current than the second pulse.

11. The testing system of claim 8, wherein the hand-held transmitter is contained within a single enclosure.

12. An arc fault circuit interrupter tester comprising:

a processor having an internally calculated clock rate, the processor generating a timing period signal for generating simulated arc fault pulses by calibrating the internally calculated clock rate based on a received synchronization signal; and

a switching circuit outputting the simulated arc fault pulses at a timing period defined by the timing period signal.

13. The arc fault circuit interrupter tester of claim 12, wherein the simulated arc fault pulses are effective to trip an arc fault circuit interrupter.

14. The arc fault circuit interrupter tester of claim 12, wherein the simulated arc fault pulses comprise a plurality of pulses of alternating polarity corresponding to alternating positive and negative phases of an AC line voltage applied to the arc fault circuit interrupter.

15. The arc fault circuit interrupter tester of claim 12, wherein the timing period is around 8.3 milliseconds.

16. The arc fault circuit interrupter tester of claim 12, wherein the simulated arc fault pulses have a peak current of greater than 100 amperes.

17. A method for testing an arc fault circuit interrupter, the method comprising:

generating a timing period signal for generating simulated arc fault pulses by calibrating an internally calculated clock rate of a processor based on a received synchronization signal; and

outputting the simulated arc fault pulses at a timing period defined by the timing period signal output by the processor.

18. The method of claim 17, wherein the simulated arc fault pulses are effective to trip an arc fault circuit interrupter.

19. The method of claim 17, wherein the simulated arc fault pulses comprise a plurality of pulses of alternating polarity corresponding to alternating positive and negative phases of an AC line voltage applied to the arc fault circuit interrupter.

20. The method of claim 17, wherein the timing period is around 8.3 milliseconds.

21. The method of claim 17, wherein the simulated arc fault pulses have a peak current of greater than 100 amperes.

22. An arc fault circuit interrupter comprising:

means for generating a timing period signal for generating simulated arc fault pulses by calibrating an internally calculated clock rate of a processor based on a received synchronization signal; and

means for outputting the simulated arc fault pulses at a timing period defined by the timing period signal output by the processor.