CIRCUITS AND METHODS FOR ALIGNMENT OF SIGNALS IN INTEGRATED CIRCUITS
First Claim
Patent Images
1. A circuit comprising:
- at least one phase lock loop to generate at least one core signal having multiple cycles within one cycle of an external signal;
a ratio decoder to decode a programming code; and
an alignment unit coupled to the at least one phase lock loop and the ratio decoder, wherein the alignment unit includes a master pulse generator to generate a master pulse based on a combination of the at least one core signal and a modified copy of the external signal to synchronize a plurality of copies of the master pulse with the external signal based on the programming code.
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Abstract
Circuits and methods align an internal signal with an external signal. A phase lock loop network receives the external signal to generate phase lock loop signals. A programmable ratio decoder provides a code. An alignment unit generates the internal signal based on at least one of the phase lock loop signals. The alignment unit aligns internal signal with the external signal based on the code.
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Citations
29 Claims
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1. A circuit comprising:
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at least one phase lock loop to generate at least one core signal having multiple cycles within one cycle of an external signal;
a ratio decoder to decode a programming code; and
an alignment unit coupled to the at least one phase lock loop and the ratio decoder, wherein the alignment unit includes a master pulse generator to generate a master pulse based on a combination of the at least one core signal and a modified copy of the external signal to synchronize a plurality of copies of the master pulse with the external signal based on the programming code. - View Dependent Claims (5)
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2. A circuit comprising:
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at least one phase lock loop to generate at least one core signal having multiple cycles within one cycle of an external signal;
a ratio decoder to decode a programming code; and
an alignment unit coupled to the at least one phase lock loop and the ratio decoder to synchronize a plurality of propagation pulses with the external signal based on the programming code, wherein the alignment unit includes a master pulse generator to generate a master pulse having a pulse width equal to one cycle of the at least one core signal.
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3. A circuit comprising:
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at least one phase lock loop to generate at least one core signal having multiple cycles within one cycle of an external signal;
a ratio decoder to decode a programming code; and
an alignment unit coupled to the at least one phase lock loop and the ratio decoder to synchronize a plurality of propagation pulses with the external signal based on the programming code, wherein the alignment unit includes a propagation pulse generator to periodically provide each of the propagation pulses to an propagation compensator of the alignment unit at a propagation interval before an occurrence of an anticipated edge of the external clock. - View Dependent Claims (4)
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6. A circuit comprising:
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at least one phase lock loop to generate at least one core signal having multiple cycles within one cycle of an external signal;
a ratio decoder to decode a programming code; and
an alignment unit coupled to the at least one phase lock loop and the ratio decoder to synchronize a plurality of propagation pulses with the external signal based on the programming code, wherein the ratio decoder includes a math unit to perform a math operation on the programming code, wherein the ratio decoder further includes a selector to select between a control value represented by a programming code and a control value resulted from the math operation.
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7. An integrated circuit comprising:
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a phase lock loop network to receive an external signal to generate at least one core signal;
a master pulse generator to generate a master pulse based on a combination of the at least core signal and a modified version of the external signal;
a propagation pulse generator coupled to the master pulse generator to generate a plurality of propagation pulses based on the master pulse;
an propagation compensator coupled to the propagation pulse generator to propagate the plurality of propagation pulses for a propagation interval to generate an internal clock signal; and
a ratio decoder coupled to the propagation pulse generator to provide at least one control value to influence a timing of the plurality of propagation pulses. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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16. A system comprising:
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a clock generator to generate an external signal;
a dynamic random access memory device coupled to receive the external signal; and
a plurality of integrated circuits coupled to receive the external signal, at least one of the plurality of integrated circuits including;
an internal signal generating unit to generate at least one core signal;
a ratio decoder to decode a programming code; and
an alignment unit coupled to the internal signal generating unit and the ratio decoder, wherein the alignment unit includes a master pulse generator to generate a master pulse based on a combination of the at least one core signal and a modified copy of the external signal to synchronize a plurality of copies of the master pulse with the external signal based on the programming code. - View Dependent Claims (18, 21)
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17. A system comprising:
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a clock generator to generate an external signal;
a dynamic random access memory device coupled to receive the clock generator; and
a plurality of integrated circuits coupled to receive the external signal, at least one of the plurality of integrated circuits including;
an internal signal generating unit to generate at least one core signal;
a ratio decoder to decode a programming code; and
an alignment unit coupled to the internal signal generating unit and the ratio decoder to synchronize a plurality of propagation pulses with the external signal based on the programming code, wherein the internal signal generating unit include includes multiple phase lock loops coupled in a cascaded configuration.
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19. A system comprising:
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a clock generator to generate an external signal;
a dynamic random access memory device coupled to receive the clock generator; and
a plurality of integrated circuits coupled to receive the external signal, at least one of the plurality of integrated circuits including;
an internal signal generating unit to generate at least one core signal;
a ratio decoder to decode a programming code; and
an alignment unit coupled to the internal signal generating unit and the ratio decoder to synchronize a plurality of propagation pulses with the external signal based on the programming code, wherein the alignment unit includes a master pulse generator to generate a master pulse having a pulse width equal to at least one cycle of the at least one core signal.
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20. A system comprising:
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a clock generator to generate an external signal, a dynamic random access memory device coupled to receive the clock generator; and
a plurality of integrated circuits coupled to receive the external signal, at least one of the plurality of integrated circuits including;
an internal signal generating unit to generate at least one core signal, a ratio decoder to decode a programming code; and
an alignment unit coupled to the internal signal generating unit and the ratio decoder to synchronize a plurality of propagation pulses with the external signal based on the programming code, wherein the alignment unit includes a propagation pulse generator to periodically provide each of the propagation pulses to an propagation compensator of the alignment unit at a propagation interval before an occurrence of an anticipated edge of the external clock.
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22. A system comprising:
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a clock generator to generate an external signal;
a dynamic random access memory device coupled to receive the clock generator; and
a plurality of integrated circuits coupled to receive the external signal, at least one of the plurality of integrated circuits including;
an internal signal generating unit to generate at least one core signal;
a ratio decoder to decode a programming code; and
an alignment unit coupled to the internal signal generating unit and the ratio decoder to synchronize a plurality of propagation pulses with the external signal based on the programming code, wherein the ratio decoder includes a logic unit to perform a math operation on the programming code, wherein the ratio decoder further includes a selector to select between a control value represented by a programming code and a control value resulted from the math operation.
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23. A method comprising:
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generating a core signal based on an external signal, the core signal having core cycles;
producing a master pulse based on a combination of the core signal and a modified version of the external signal;
producing a plurality of propagation pulses including a first propagation pulse and a group of subsequent propagation pulses, wherein the first propagation pulse is produced at an initial interval after the master pulse is produced; and
propagating the plurality of propagation pulses for a propagation interval to align the plurality of propagation pulses with the external signal. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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Specification